參數(shù)資料
型號： MPC745CVT350LE
廠商： Freescale Semiconductor
文件頁數(shù)： 15/56頁
文件大小： 0K
描述： MCU HIP4DP 350MHZ 255-PBGA
標準包裝： 60
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 350MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 255-BBGA，F(xiàn)CBGA
供應商設備封裝： 255-FCPBGA（21x21）
包裝： 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
22
Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.5
IEEE 1149.1 AC Timing Specifications
Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through
Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC755.
Figure 11. AC Test Load for the JTAG Interface
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 3)
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
016
MHz
TCK cycle time
tTCLK
62.5
—
ns
TCK clock pulse width measured at 1.4 V
tJHJL
31
—
ns
TCK rise and fall times
tJR, tJF
02
ns
TRST assert time
tTRST
25
—
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
—
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
15
12
—
ns
3
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
—
4
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDH
tJLOH
25
12
—
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 11).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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