- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4048 > MPC745CVT350LE (Freescale Semiconductor)MCU HIP4DP 350MHZ 255-PBGA PDF資料下載
參數(shù)資料
| 型號： | MPC745CVT350LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/56頁 |
| 文件大小： | 0K |
| 描述： | MCU HIP4DP 350MHZ 255-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC7xx |
| 處理器類型： | 32-位 MPC7xx PowerPC |
| 速度： | 350MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 255-FCPBGA（21x21） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
20
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
Figure 8. L2 Bus Input Timing Diagrams
L2SYNC_IN to high impedance:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOZ
—
2.4
2.6
2.8
3.0
ns
3, 5
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the
signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous BurstRAMs,
L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15] = 11 is
recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more
information, refer to Section 10.2, “Part Numbers Not Fully Addressed by This Document.”
Table 12. L2 Bus Interface AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN
L2 Data and Data
VM
VM = Midpoint Voltage (L2OVDD/2)
tDVL2CH
tDXL2CH
tL2CR
tL2CF
Parity Inputs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC745CPX350LE | MCU HIP4DP 350MHZ 255-PBGA |
| MPC745BVT350LE | IC MPU PPC 350MHZ 255-FCPBGA |
| FMM44DSEN-S243 | CONN EDGECARD 88POS .156 EYELET |
| MC68302CRC16C | IC MPU NETWORK 16MHZ 132-PQA |
| MPC8533EVTARJA | MPU POWERQUICC 783-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC750 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MPC750 RISC Microprocessor |
| MPC75-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75201J | 功能描述:厚膜電阻器 - 透孔 MPC7 200R 5% RoHS:否 制造商:Caddock 電阻:27 kOhms 容差:1 % 功率額定值:8 W 溫度系數(shù):50 PPM / C 系列:MS 端接類型:Axial 電壓額定值:2 kV 工作溫度范圍:- 15 C to + 275 C 尺寸:8.89 mm Dia. x 23.11 mm L 封裝:Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。