參數(shù)資料
型號： MPC5606SCLQ6R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 94/136頁
文件大?。?/td> 858K
代理商： MPC5606SCLQ6R
MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
60
NOTE
RAM data retention is guaranteed with VDD12 not below 1.08 V.
3.4.2
Connecting power supply pins: What to do and what not to do
Do:
— Have all power/ground supplies connected on the board from a strong supply source rather than weak voltage
divider sources unless there is “NO IO activity” in the section
— Meet the supply specifications for max / typical operating conditions to guarantee correct operation
— Place the decoupling near the supply/ground pin pair for EMI emissions reduction
— Route high-noise supply/ground away from sensitive signals (for example, ADC channels must be away from
SMD supply/motor pads)
VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with
respect to ground (VSSE_B)
—4.5
5.5
V
VDDE_C
7 SR C Voltage on VDDE_C (I/O supply) pin with
respect to ground (VSSE_C)
—4.5
5.5
V
VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with
respect to ground (VSSE_E)
—4.5
5.5
V
VDDMA SR C Voltage on VDDMA (stepper motor supply)
pin with respect to ground (VSSMA)
—4.5
5.5
V
VDDMB SR C Voltage on VDDMB (stepper motor supply)
pin with respect to ground (VSSMB)
—4.5
5.5
V
VDDMC SR C Voltage on VDDMC (stepper motor supply)
pin with respect to ground (VSSMC)
—4.5
5.5
V
VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin
with respect to VSS
—0
0
V
VLCD
SR C Voltage on VLCD (LCD supply) pin with
respect to VSS
—0
VDDE_A +0.3
V
TVDD
SR C VDD slope to ensure correct power up
—
3
10–6
0.25
V/s
TA
SR C Ambient temperature under bias
—
40
105
°C
TJ
SR C Junction temperature under bias
—
40
150
°C
1 100 nF capacitance needs to be provided between V
DDA/VSSA pair.
2 Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical
characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.
3 10 F capacitance must be connected between V
DDR and VSS12. This is required because of sharp surge due to
external ballast.
4 V
DD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC.
5 100 nF capacitance needs to be provided between each V
DD/VSS pair
6 V
SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
7 V
DDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV.
Table 16. Recommended operating conditions (5.0 V) (continued)
Symbol
C
Parameter
Conditions
Value
Unit
Min
Max
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