參數(shù)資料
型號(hào)： MPC5606SCLQ6R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件頁數(shù)： 13/136頁
文件大小： 858K
代理商： MPC5606SCLQ6R
MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
11
4 slave ports:
— 1 flash port dedicated to the CPU
— Platform SRAM
— QuadSPI serial flash controller
— 1 slave port combining:
–
Flash port dedicated to the Display Control Unit and eDMA module
–
Graphics SRAM
–
Peripheral bridge
32-bit internal address bus, 32-bit internal data bus
1.6.4
Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source
and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing
the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The
eDMA module provides the following features:
16 channels support independent 8-, 16- or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain constant
Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
DMA transfers possible between system memories, QuadSPI, DSPIs, I2C, ADC, eMIOS and General Purpose I/Os
(GPIOs)
Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to
a total of 64 potential request sources.
1.6.5
Inter-IC communications module (I2C)
The I2C module features the following:
Up to four I2C modules supported
Two-wire bi-directional serial bus for on-board communications
Compatibility with I2C bus standard
Multimaster operation
Software-programmable for one of 256 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
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