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參數(shù)資料
| 型號： | MPC5566MZP144 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 53/66頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 3MB FLASH 416PBGA |
| 標(biāo)準(zhǔn)包裝： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 144MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 256 |
| 程序存儲器容量： | 3MB（3M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 40x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 416-BBGA |
| 包裝： | 托盤 |
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Revision History for the MPC5566 Data Sheet
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
57
5.3
Information Changed Between Revisions 0.0 and 1.0
The following table lists the global changes made throughout the document, as well as the changes to
sections of text not contained in a figure or table.
Table 34. Global and Text Changes Between Rev. 0.0 and 1.0
Location
Description of Changes
Global Changes
Third paragraph and throughout the document, replaced:
kilobytes with KB.
megabytes with MB.
Put overbars on the following signals: BB, BG, BR, BDIP, OE, TA, TEA, TS,
Changed WE[0:3]/BE[0:3] to WE/BE[0:3].
Added a 144 MHz system frequency option for the MPC5566 microcontroller.
First paragraph, text changed from “ based on the PowerPC Book E architecture” to “built on the Power
Architecture embedded technology.”
Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
Added new fourth paragraph about VLE feature.
Paragraph nine: changed “the MPC5566 has an on-chip 20-channel enhanced queued analog-to-digital
converter (eQADC)” to “has an on-chip 40-channel dual enhanced queued”
Added paragraph about the Fast Ethernet Controller directly after the System Integration Unit paragraph.
Added the sentence directly preceding Table 1: ‘Unless noted in this data sheet, all specifications apply from
TL to TH.’
3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
From:
‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
(1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the
device by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the
RESET power pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or
VDDEH6 supplies, but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only
applies during power up. VDD33 has no lead or lag requirements when powering down.’
To:
‘When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the
VDD33 lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state
when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than
the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.’
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