OPERATIONAL MODES HBF— HB1:4 Failure Bi" />
參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 40/63頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HBF— HB1:4 Failure Bit
This read only bit is set if a fail condition on one of the half-
bridge outputs is present.
1 = HB1:4 pin over-current fail
0 = HB1:4 normal operating
Figure 28. HBF Flag Generation
ECF— EC pin Failure Bit
This read only bit is set if a fail condition on the
electrochrome output is present
1 = EC pin fail
0 = EC normal operating
Figure 29. ECF Flag Generation
WINDOW WATCHDOG
The window watchdog is to supervise the device and to
recover from (e.g. code runaways) or similar conditions.
The use of a window watchdog adds additional safety as
the watchdog clear has not only to occur, but to be done at a
certain time frame / window.
Normal Mode
The window watchdog function is only available in Normal
mode, and is halted in Stop and Sleep mode. Upon setting
the WDRE bit, the watchdog functionality is activated. Once
this function is enabled, it is not possible to disable it via
software. Reset clears the WDRE bit.
To prevent a Watchdog reset, the Watchdog timer has to
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission, with the rising
edge of the SS signal.
If the watchdog is enabled, it will generate a system reset
when the timer has reached its end value, or if a watchdog
reset (WDRST) has occurred in the closed window.
The watchdog period can be selected with 2 bits in the
WDCTL, in order to get 10 ms, 20 ms, 40 ms, and 80 ms
periods.
Figure 30. Window Watchdog Period
Stop Mode
Operations of the watchdog function is ceased in stop
mode (counter/oscillator stopped). After a wake-up, the
watchdog timer is automatically cleared, in order to give the
MCU the full time to reset the watchdog.
Sleep Mode
Operations of the watchdog function are halted in sleep
mode. Due to the main voltage regulator asserting an LVR
reset, the Watchdog functionality is disabled, and the WDRE
bit is cleared as soon as sleep mode is entered. To reenable
this function bit WDRE has to be set after wake-up.
Watchdog Control Register (WDCTL)
WDRE - Watchdog Reset Enable Bit
This read/write (write once) bit activates the watchdog The
WDRE can only be set and can’t be cleared by software.
Reset clears the WDRE bit.
1 = Watchdog enabled
0 = Watchdog disabled
WDP1:0 - Watchdog Period Select Bits
This read/write bit select the clock rate of the Watchdog.
Reset clears the WDP1:0 bits.
HB1OCF
HB2OCF
HB3OCF
HB4OCF
HBF
ECOCF
ECOLF
ECF
Register Name and Address: WDCTL - $0B
Bit7
6
5
4
3
2
1
Bit0
Read WDR
E
WDP
1
WDP
0
000
0
Write
WDR
ST
Reset
0
Table 12. Watchdog Period Selection Bits
WDP1
WDP0
Mode
0
80 ms window watchdog period
0
1
40 ms window watchdog period
Window closed
no watch dog clear allowed
Window open
for watch dog clear
WD timing x 50%
WD period ( timing selected by Bits WDP1:0)
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