OPERATIONAL MODES RESET SOURCE High Temper" />
參數(shù)資料
型號(hào)： MM908E622ACDWB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 24/63頁(yè)
文件大小： 0K
描述： IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 自動(dòng)鏡像控制
核心處理器： HC08
程序存儲(chǔ)器類型： 閃存（16 kB）
控制器系列： 908E
RAM 容量： 512 x 8
接口： SCI，SPI
輸入/輸出數(shù)： 12
電源電壓： 9 V ~ 16 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 54-BSSOP（0.295"，7.50mm 寬）裸露焊盤(pán)
包裝： 管件
供應(yīng)商設(shè)備封裝： 54-SOICW-EP
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by the HTRD bit in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part, in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The Watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
Watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. When the voltage
falls below a certain threshold, it will pull down the RST_A
pin. Reset is flagged by the LVR bit in the Reset Status
Register. An LVR event will reset all register in the SPI,
excluding the RSR.
Power On Reset
The POR is related to the internal 5.0 V supply. When the
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all registers
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for tRST after the VDD has reached its nominal value (above
LVR Threshold). Also see Figure 10, page 19).
Reset pin / external Reset
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
RESET STATUS REGISTER
This register contains five flags that show the source of the
last reset. A power on reset sets the POR bit and clears all
other bits in the Reset Status Register. All bits can be cleared
by writing a one to the corresponding bit. Uncleared bits
remain set as long as they are not cleared by a power on
reset or by software.
In addition the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either by
LIN bus activity or an event on the L0 wake-up input pin.
POR— Power On Reset Bit
This read/write bit is set after power on. The bit is cleared
by writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing a logic
“1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to watchdog timeout or a
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value. Bit
is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. Bit is cleared by writing a logic “1” to this location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. Bit is cleared by writing a logic “1” to this location.
1 = Wake-up due to L0 pin
0 = no Wake-up due to L0 pin
Register Name and Address: RSR - $0D
Bit7
6
5
4
3
2
1
Bit0
Read
POR
PINR
WDR
HTR
LVR
0
LINWF LOWF
Write
POR
1
0
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