OPERATIONAL MODES HTIS0-1 — High Temperatu" />
參數(shù)資料
型號(hào): MM908E622ACDWB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 39/63頁(yè)
文件大小: 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動(dòng)鏡像控制
核心處理器: HC08
程序存儲(chǔ)器類(lèi)型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤(pán)
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HTIS0-1 — High Temperature Interrupt Shutdown Bits
This read/write bit selects the power stage behavior at
High Temperature Interrupt (HTI). Reset clears the HTIS0-1
bits.
The HTIS0 bit selects the behavior of the high side HS1:3
and the high side FET of the half-bridges HB1:4.
1 = automatic HTI shutdown of the high side drivers
disabled
0 = automatic HTI shutdown of the high side drivers
enabled
The HTIS1 bit selects the behavior of the low side drivers
of the half-bridges HB1:4.
1 = automatic HTI shutdown of the low side drivers
disabled
0 = automatic HTI shutdown of the low side drivers
enabled
The user must take care to protect the device against
thermal destruction!
VIS — Over /Under-voltage Interrupt Shutdown
This read/write bit selects the power stage behavior at LVI/
HVI. Reset clears the VIS bit.
1 = automatic LVI/HVI shutdown disabled
0 = automatic LVI/HVI shutdown enabled
SRS0-1 — LIN Slew rate Select Bits
These read/write bits enable the user to select the
appropriate LIN slew rate for different Baudrate
configurations. Reset clears the SRS1:0 bits.
The high speed slew rates are used, for example, for
programming via the LIN, and are not intended for use in the
application.
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
This read only bit is set if the LIN transmitter operates in
the current limitation region. Due to excessive power
dissipation in the transmitter, the driver will be automatically
turned off after a certain time.
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
HTIF— Over-temperature Status Bit
This read only bit is a copy of the HTIF bit in the Interrupt
Flag register
1 = over-temperature condition
0 = no over-temperature condition
VF — Voltage Failure Bit
This read only bit indicates that the supply voltage was out
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register are set.
1 = low/high voltage condition detected
0 = no voltage failure condition detected
Figure 26. VF Flag Generation
H0F — H0 Failure Bit
This read only bit is a copy of the H0OCF bit in the H0/L0
Status and Control Register (HLSCTL)
1 = over-current detected on H0
0 = no over-current on H0
HVDDF— HVDD Failure Bit
This read only bit is a copy of the HVDDOCF bit in the High
Side Status register
1 = HVDD pin fail
0 = HVDD normal operating
HSF— HS1:3 Failure Bit
This read only bit is set if a fail condition on one of the high
side outputs is present
1 = HS1:3 pin fail
0 = HS1:3 normal operating
Figure 27. HSF Flag Generation
Table 11. LIN Slew Rate Selection Bits
SRS1
SRS0
Slew rate
0
Initial Slew Rate (20kBaud)
0
1
High Speed II (8x)
1
0
Slow Slew Rate (10kBaud)
1
High Speed I (4x)
Register Name and Address: SYSSTAT - $0C
Bit7
6
5
4
3
2
1
Bit0
Read
LINC
L
HTIF
VF
H0F
HVD
DF
HSF
HBF
ECF
Write
Reset
0
LVIF
HVIF
VF
HS3OCF
HS2OCF
HS1OCF
HSF
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