LOGIC COMMANDS AND REGISTERS Analog Die Sy" />
參數(shù)資料
型號: MM908E621ACDWB
廠商: Freescale Semiconductor
文件頁數(shù): 42/60頁
文件大?。?/td> 0K
描述: IC QUAD HALF BRDG TRPL SW 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
908E621
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Die System Trim Values
For improved application performance, and to ensure the
outlined datasheet values, the analog die needs to be
trimmed. For this purpose, 3 trim values are stored in the
Flash memory at addresses $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
copy $FDC4 into SYSTRIM1 register $0F
copy $FDC5 into SYSTRIM2 register $10
copy $FDC6 into SYSTRIM3 register $11
Note: These values must be copied to the respective SPI
register after a reset, to ensure proper trimming of the device.
System Test Register (SYSTEST)
The System Test Register is reserved for production
testing and is not allowed to be written to.
System Trim Register 1 (SYSTRIM1)
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits
These read/write bits allow changes to the filter time (for
capacitive load) for HVDD over-current detection. Reset
clears the HVDDT1:0 bits and sets the delay to the maximum
value.
ITRIM3:0 - IRef Trim Bits
These write only bits are for trimming the internal current
references IRef (also A0, A0CST). The provided trim values
have to be copied into these bits after every reset. Reset
clears the ITRIM3:0 bits.
System Trim Register 2 (SYSTRIM2)
CRHBHC1:0 - Current Recopy HB1:2 Trim Bits
These write only bits are for trimming the current recopy of
the half-bridge HB1 and HB2 (CSA=0). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHBHC1:0 bits.
CRHB5:3 - Current Recopy HB3:4 Trim Bits
These write only bits are for trimming the current recopy of
the half-bridge HB3 and HB4 (CSA=1). The provided trim
values have to be copied into these bits after every reset.
Reset clears the CRHB5:3 bits.
Register Name and Address: SYSTEST - $0E
Bit7
6
5
4
3
2
1
Bit0
Read
reserved
Write
Reset
0
Note: do not write to the reserved bits
Register Name and Address: IBIAS - $0F
Bit7
6
5
4
3
2
1
Bit0
Read
HVDDT1
HVDDT0
0
reserved
0
reserved
ITRIM3 ITRIM2 ITRIM1
ITRIM0
Write
Reset
0
Note: do not change (set) the reserved bits
Table 14. HVDD Over-current Shutdown Selection Bits
HVDDT1
HVDDT0
Typical Delay
0
950
μs
0
1
536
μs
1
0
234
μs
1
78
μs
Table 15. IRef Trim Bits
itrim3
itrim2
itrim0
Adjustment
0
1
2%
0
1
0
4%
0
1
8%
0
1
0
12%
0
1
0
1
-2%
0
1
0
-4%
0
1
-8%
1
0
-12%
Register Name and Address: IFBHBTRIM - $10
Bit7
6
5
4
3
2
1
Bit0
Read
0
Write CRHBHC1 CRHBHC0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0
Reset
0
Table 16. Current Recopy Trim for HB1:2 (CSA=0)
CRHBHC1
CRHBHC0
Adjustment
0
1
-10%
1
0
5%
1
10%
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