參數(shù)資料
型號(hào): MM82PC12N
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: 8-Bit Input/Output Port
中文描述: 8 I/O, PIA-GENERAL PURPOSE, PDIP24
封裝: PLASTIC, DIP-24
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 189K
代理商: MM82PC12N
Connection Diagrams
Dual-In-Line Package
TL/C/5596–10
Top View
Order Number MM82PC12J or N
See NS Package Number J24A or
N24A
Plastic Chip Carrier
TL/C/5596–12
Top View
Order Number MM82PC12V
See NS Package Number V28A
Logic Diagram
TL/C/5596–11
Logic Table A
STB
MD
DS
1
#
DS
2
Data Out
Equals
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
TRI-STATE
TRI-STATE
Data Latch
Data Latch
Data Latch
Data In
Data In
Data In
Note:
CLR
K
resets data latch to the output low state. The data latch
clock is level sensitive, a low level clock latches the data.
Logic Table B
DS
1
#
DS
2
CLR
STB
Q
*
INT
0 RESET
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
K
0
0
1 RESET
0
*
Internal Service Request flip-flop.
5
相關(guān)PDF資料
PDF描述
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