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參數(shù)資料
| 型號： | MM82PC12N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit Input/Output Port |
| 中文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 189K |
| 代理商： | MM82PC12N |
Propagation Delays
Figure 1 illustrates the calculations of a more useful propa-
gation delay. The figure uses a 5V supply with a tolerance of
g
10%, ambient temperature of
a
25
§
C, and a load capaci-
tance of 100 pF. The AC Characteristics table depicts t
PD
,
at 5V, 25
§
C, equalling 25 ns. Use the graph inFigure 1 to get
the degradation multiple for 150 pF. The number shown is
1.09. The adjusted propagation delay is, therefore 25
c
1.09 or 27 ns.
TL/C/5596–7
*
Including jig and probe capacitance.
Output Test Circuit
for Propagation Delays
TL/C/5596–8
TL/C/5596–9
FIGURE 1. Normalized Typical Propagation Delay vs.
Load Capacitance
Pin Descriptions
The following describes the function of all the MM82PC12
input/output pins. Some of these descriptions reference in-
ternal circuits.
INPUT SIGNALS
Device Select (DS
1
, DS
2
:
When DS
1
is low and DS
2
is high,
the device is selected. The output buffers are enabled and
the
service
request
flip-flop
(cleared) when the device is selected.
is
asynchronously
reset
Mode (MD):
When MD is high (output mode), the output
buffers are enabled and the source of the data latch clock
input is the device selection logic (DS
1
#
DS
2
). When MD is
low (input mode), the state of the output buffers is deter-
mined by the device selection logic (DS
1
#
DS
2
) and the
source of the data latch clock input is the strobe (STB) in-
put.
Strobe (STB):
STB is used as the data latch clock input
when the mode (MD) input is low (input mode). STB is also
used to synchronously set the service request flip-flop,
which is negative edge triggered.
Data In (DI
1
–DI
8
):
Data In is the 8-bit data input to the data
latch, which consists of eight D-type flip-flops incorporating
a level sensitive clock. While the data latch clock input is
high, the Q output of each flip-flop follows the data input.
When the clock input returns low, the data latch stores the
data input. Clear (CLR) is only effective when the clock is
low (latch in the latched state).
Clear (CLR):
When CLR is low, the data latch is reset
(cleared) if the clock is also low. The clock input high over-
rides the clear (CLR) input data latch reset. CLR being low
also resets the service request flip-flop. The service request
flip-flop is in the non-interrupting state when reset.
OUTPUT SIGNALS
Interrupt (INT):
The interrupt pin goes low (interrupting
state) when either the service request flip-flop is synchro-
nously set by the strobe (STB) input or the device is select-
ed.
Data Out (DO
1
–DO
8
):
Data Out is the 8-bit data output of
data buffers, which are TRI-STATE, non-inverting stages.
These buffers have a common control line that either en-
ables the buffers to transmit the data from the data latch
outputs or disables the buffers by placing them in the high-
impedance state.
Reliability Information
Gate Count 108
Transistor Count 248
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM82PC12NI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MM82PC12NI/883 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Input/Output Port |
| MM82PC12NI/A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Input/Output Port |
| MM82PC12NM/883 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Input/Output Port |
| MM82PC12NM/A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Input/Output Port |
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