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參數(shù)資料
| 型號(hào)： | MM54C32N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quad 2-Input OR Gate |
| 中文描述： | CMOS SERIES, QUAD 2-INPUT OR GATE, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | MM54C32N |
TL/F/5881
M
February 1988
MM54C32/MM74C32 Quad 2-Input OR Gate
General Description
Employing complementary MOS (CMOS) transistors to
achieve low power and high noise margin, these gates pro-
vide the basic functions used in the implementation of digital
integrated circuit systems. The N- and P-channel enhance-
ment mode transistors provide a symmetrical circuit with
output swings essentially equal to the supply voltage. This
results in high noise immunity over a wide supply voltage
range. No DC power other than that caused by leakage cur-
rent is consumed during static conditions. All inputs are pro-
tected against static discharge damage.
Features
Y
Wide supply voltage range
3.0V to 15V
Y
Guaranteed noise margin
1.0V
Y
High noise immunity
0.45V V
CC
(typ.)
fan out of 2
driving 74L
Y
Low power
TTL compatibility
Connection Diagram
Dual-In-Line Package
TL/F/5881–1
Top View
Order Number MM54C32 or MM74C32
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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