
ML671000 User’s Manual
Chapter 11 Universal Serial Bus Device Controller (USBC)
11-41
11.5.
Power Conservation Function
This function allows the USB device controller to conserve power by shifting to a suspended state
that cuts off its internal clock supply until a controller resume signal from the bus or a reset restores
that clock signal.
Shifting the CPU to the STOP mode while the USB device controller is in this suspended state
greatly enhances the power savings.
The following procedure gives the control flow for using this combination.
1.
Set the SSIE and UBRIE bits in INTBLEN1 to "1" to enable suspended state interrupts and
USB bus resets. Set the OSCEN bit in AWKCON to "1" to give the USB device controller
control over the clock.
2.
Set the interrupt levels for USBSINT and USBEVENT to at least 1. Note that the USBEVENT
interrupt level must be higher than that for USBSINT.
3.
For USBSINT interrupt requests, read the SINTIS bit in AWKCON or the SSIS bit in
INTSTAT1 to confirm that the interrupt request represents a suspended state interrupt request
and then reset IRR0[0] to "0" in the interrupt handler.
4.
If there are any DMA or serial transfers in progress, shift to STOP mode. (Note that doing so
requires either clearing all interrupt requests with interrupt levels of 1 or higher or resetting
their interrupt levels to 0.)
Shifting to STOP mode cuts clock signals to the CPU and all built-in peripherals except
the USB device controller.
The USB device controller continues to receive a clock signal. When the USB bus enters
its inactive state, the USB device controller shuts down the clock oscillator and phase-
locked loop, shifting to the SUSPEND state. A resume or reset signal from the USB bus
causes the USB device controller to restart the clock oscillator and phase-locked loop and
resume detecting signals. If signal detection reveals that the USB bus has returned to its
idle state, the USB device controller shuts down the clock oscillator and phase-locked loop
to return to the SUSPEND state.
If the USB device controller detects a resume or reset signal, however, it generates a
wake-up interrupt request and asserts USBSINT.
If the signal is a reset, the USB device controller simultaneously generates a USB bus reset
start interrupt request and asserts USBEVENT.
5.
The USBSINT signal releases the chip from the STOP mode. The CPU and built-in peripherals
resume operation after the clock stabilization interval specified in CKWTCON. The chip is then
ready to accept the USBEVENT and USBSINT interrupt requests.
If there is a USBEVENT interrupt request, the interrupt handler for the USB bus reset start
interrupt sets IRR0[0] to "0" to clear the USBSINT interrupt request.
If there is a USBSINT interrupt request, read the SINTIS bit in AWKCON or the SSIS bit
in INTSTAT1 to confirm that the interrupt request represents a wake-up interrupt request
and branch to the wake-up routine.
Note: If USBSINT has an interrupt level of 1 or higher, there is a USBSINT interrupt request after
every bus reset request.