
ML671000 User’s Manual
Chapter 11 Universal Serial Bus Device Controller (USBC)
11-37
2.
Transmitting
Figure 11-50 shows FIFO buffer operation for a transmit operation. For a Bulk transmit transfer, the
FIFO buffers switch roles in the following situations.
-
There is transmit data in only one FIFO buffer when the transmit packet ready bit is set to
"1." In this case, setting the transmit packet ready bit does not set that bit.
-
An ACK from the host indicates that the last data was sent successfully.
IN token
packet
ACK
Data packet A
Bus sequence
Write data packet A
Data packet A transmitted
Write
possible
FIFO_1 state
Write
possible
Write data packet B
Transmit
possible
FIFO_2 state
IN token
packet
Transmit packet ready
bit
Set transmit packet ready bit to
indicate end of packet A write
Transfer request signal
(DREQ)
Assert
Waiting to
transmit
ACK
Assert
Transmit not possible (no data)
Waiting to transmit
Write possible
Data packet B transmitted
Write data packet C
Transmit not
possible (no data)
Set transmit packet ready bit to
indicate end of packet B write
Data packet B
Figure 11-50: Paired FIFO buffers Operation for Bulk Transfer Transmit
11.3.2. Isochronous Transfers
With isochronous transfers, the FIFO buffers switch roles every time that the USB device controller
receives a start of frame (SOF) packet regardless of the direction (receive or transmit). There is
therefore no need to reset the receive packet ready bit when a data read is complete or to set the
transmit packet ready bit when a data write is complete.
Note that these data reads and writes must be complete before the USB device controller receives a
start of frame (SOF) packet. Otherwise, this automatic FIFO buffer switching during a read or write
leads to unreliable results.
Figure 11-51 shows FIFO buffer operation for an isochronous receive operation; Figure 11-52, for a
transmit operation.
OUT
token
packet
Data packet A
SOF
packet
Bus sequence
Read not
possible(no data)
Data packet A stored
Read
possible
FIFO_1 state
FIFO_2 state
Read data packet A
Transfer request signal
(DREQ)
OUT
token
packet
SOF
packet
OUT
token
packet
SOF
packet
Storage complete
Data storage
possible
SOF interrupt status
Clear status
Assert
Data storage
possible
Read not possible(no data)
Data storage
possible
Data packet B
Data packet B stored
Read not possible(no data)
Storage complete
Clear status
Data storage
possible
Read
possible
Data packet C
Data packet B stored
Read data packet B
Figure 11-51: Paired FIFO buffers Operation for Isochronous Receive