參數(shù)資料
型號: ML2724DH
英文描述: 2.4GHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
中文描述: 2.4GHz的低IF 1.5Mbps的FSK收發(fā)器最終數(shù)據(jù)表
文件頁數(shù): 20/26頁
文件大?。?/td> 864K
代理商: ML2724DH
ML2724
RD0 - Register 0, Bit 3
Reference Divide:
This bit sets the reference divider from the FREF pin to the reference input of the PLL
phase/frequency detector to either 9 or 18 (see Table 7).
RD0
REFERENCE
DIVISION
FREF XTAL
FREQ
PLL REF
FREQ
0
9
6.144 MHz
682.67KHz
1
18
12.288 MHz
682.67KHz
Table 7: Reference Frequency Select
AOUT - Register 0, Bit 4
Analog Output Mode:
This bit changes the function of the AOUT pin between an analog data output to transmit power
control (see Table 8).
AOUT
AOUT PIN FUNCTION
0
Transmit Power Control
1
Data Filter Analog Output
Table 8: AOUT Function Select
TXCW - Register 0, Bit 6
Transmit Continuous Wave:
This bit produces a continuous wave (CW) transmitter output for product test when
RXON is low (see Table 9).
TXCW
TRANSMIT MODULATION
0
FSK Modulation
1
CW – No Modulation
Table 9: Transmit Modulation Mode
TPC - Register 0, Bit 7
Transmit Power Control:
When the AOUT bit is low, this bit controls the state of the open-drain output pin. Although
this bit can be changed at any time, the AOUT pin only changes state at the falling edge of RXON (see Table 10).
TPC
TPC PIN STATE
0
High Impedance
1
Pulled to Ground
Table 10: TPC Pin State
TXM - Register 0, Bit 8
Transmit Mode:
This bit controls the TX RF buffer state timing mode. It must be reset to 0 for normal operation (see
Table 11).
TXM
TXRF BUFFER BEHAVIOR
0
RF Output Always On in TX Mode
1
RF Output Follows PAON
Table 11: TXM Mode
DS2724-F-01
FINAL DATASHEET
APRIL 2003
20
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