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參數(shù)資料
| 型號： | ML2252 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | μP Compatible 8-Bit A/D Converters with 2-Channel Multiplexer(具有雙通道多路轉(zhuǎn)換器的微處理器兼容的8位A/D轉(zhuǎn)換器) |
| 中文描述： | 微處理器兼容的8位A / D轉(zhuǎn)換器，帶有2通道多路復用器（具有雙通道多路轉(zhuǎn)換器的微處理器兼容的8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 202K |
| 代理商： | ML2252 |
ML2252, ML2259
7
TYPICAL PERFORMANCE CURVES
(Continued)
Figure 3. Linearity Error vs V
REF
Voltage
Figure 4. Unadjusted Offset Error vs V
REF
Voltage
1.0 FUNCTIONAL DESCRIPTION
1.1 MULTIPLEXER ADDRESSING
The ML2252 and ML2259 contain a single ended analog
multiplexer. A particular input channel is selected by
using the address decoder. The relationship between the
address inputs, ADDR0–ADDR2, and the analog input
selected is shown in Table 1. The address inputs are
latched into the decoder on the rising edge of the address
latch signal ALE.
ML2252
SELECTED
ADDRESS
INPUT
0
1
ANALOG CHANNEL
CH0
CH1
ML2259
SELECTED
ADDRESS INPUT
ADDR2
ADDR1
ANALOG CHANNEL
ADDR0
CH0
0
0
0
CH1
0
0
1
CH2
0
1
0
CH3
0
1
1
CH4
1
0
0
CH5
1
0
1
CH6
1
1
0
CH7
1
1
1
Table 1. Multiplexer Address Decoding
1.2 A/D CONVERTER
The A/D converter uses successive approximation to
perform the conversion. The converter is composed of the
successive approximation register, the DAC and the
comparator.
The DAC generates the precise levels that determine the
linearity and accuracy of the conversion. The DAC is
composed of a capacitor upper array and a resistor lower
array. The capacitor upper array generates the 4 MSB
decision levels while the series resistor lower array
generates the 4 LSB decision levels. A switch decoder tree
is used to decode the proper level from both arrays.
The capacitor/resistor array offers fast conversion, superior
linearity and accuracy since matching is only required
between 2
4
= 16 elements (as opposed to 2
8
= 256
elements in conventional designs). And since the levels are
based on the ratio of capacitors to capacitors and resistors to
resistors, the accuracy and long term stability of the
converter is improved. This also guarantees monotonicity
and no missing codes, as well as eliminating any linearity
temperature or power supply dependence.
The successive approximation register is a digital block
used to store the bit decisions from the conversion.
The comparator design is unique in that it is fully
differential and auto zeroed. The fully differential
architecture provides excellent noise immunity, excellent
power supply rejection, and wide common mode range. The
comparator is auto zeroed at the start of each conversion in
order to remove any DC offset and full scale gain error, thus
improving accuracy and linearity.
1
0.75
0.5
0.25
0
0
1
2
3
4
5
V
REF
(V
DC
)
L
25°C
V
CC
= 5V
f
CLK
= 1.46MHz
2
1.5
1
0.5
0
0
1
2
3
4
5
V
REF
(V
DC
)
O
V
CC
= 5V
V
IN
= 0V
f
CLK
= 1.46MHz
T
A
= 25°C
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