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參數(shù)資料
| 型號(hào)： | ML2252 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | μP Compatible 8-Bit A/D Converters with 2-Channel Multiplexer(具有雙通道多路轉(zhuǎn)換器的微處理器兼容的8位A/D轉(zhuǎn)換器) |
| 中文描述： | 微處理器兼容的8位A / D轉(zhuǎn)換器，帶有2通道多路復(fù)用器（具有雙通道多路轉(zhuǎn)換器的微處理器兼容的8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大小： | 202K |
| 代理商： | ML2252 |
ML2252, ML2259
5
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC and Dynamic Performance Characteristics (Note 5)
t
ACQ
f
CLK
t
C
SNR
Sample and Hold Acquisition
1/2
1/f
CLK
kHz
Clock Frequency
10
1460
Conversion Time
8.5
8.5 + 250ns
1/f
CLK
dB
Signal to Noise Ratio
V
IN
= 51kHz, 5V sine.
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of f
SAMPLING
V
IN
= 51kHz, 5V sine.
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz).
THD is sum 2, 3, 4, 5 harmonics
relative to fundamental
47
THD
Total Harmonic Distortion
–60
dB
IMD
Intermodulation Distortion
V
IN
= f
A
+ f
B
. f
A
= 49kHz, 2.5V sine.
f
B
= 47.8kHz, 2.5V sine,
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz). IMD is (f
A
+ f
B
),
(f
A
– f
B
), (2f
A
+ f
B
), (2f
A
– f
B
), (f
A
+ 2f
B
),
(f
A
– 2f
B
) relative to fundamental
V
IN
= 0 to 50kHz. 5V sine relative
to 1kHz
–60
dB
FR
Frequency Response
0.1
dB
t
DC
t
EOC
t
WS
t
SS
t
WALE
Clock Duty Cycle
(Note 6)
40
60
%
End of Conversion Delay
1/2
1/2 + 250ns
1/f
CLK
ns
Start Pulse Width
50
Start Pulse Setup Time
Synchronous only, (Note 7)
40
ns
Address Latch Enable
Pulse Width
50
ns
t
S
t
H
t
H1, H0
Address Setup
0
ns
Address Hold
50
ns
Output Enable for DB0–DB7
Figure 1, C
L
= 50pF
Figure 1, C
L
= 10pF
Figure 1, C
L
= 50pF
Figure 1, C
L
= 10pF
100
ns
50
ns
t
1H, 0H
Output Disable for DB0–DB7
100
ns
50
ns
C
IN
C
OUT
Capacitance of Logic Input
5
pF
Capacitance of Logic Outputs
10
pF
Note 1:
Note 2:
Note 3:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
For –V
REF
V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5V) can
cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an
absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage of 4.900V
DC
over temperature variations, initial tolerance and loading.
Leakage current is measured with the clock not switching.
C
L
= 50pF, timing measured at 50% point.
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60μs.
The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,
start conversion will have an uncertainty of one clock pulse.
Note 4:
Note 5:
Note 6:
Note 7:
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