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參數(shù)資料
| 型號： | MK1581-01GILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GENERATOR T1/E1 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 無 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.048MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR
3
MK1581-01
REV F 051310
Functional Description
The MK1581-01 is a clock generator IC that generates a T1
or E1 reference clock directly from an internal VCXO circuit
that works in conjunction with an external quartz crystal.
The VCXO output frequency and phase is controlled by an
internal PLL (Phase Locked Loop) circuit, enabling the
device to perform clock regeneration from an 8 kHz input
reference clock.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK1581-01 is able to
generate a low jitter, low phase-noise output clock. The low
bandwidth capability of the PLL circuit serves to provide
input clock jitter attenuation and enables stable operation
with the low frequency input reference clock.
The internal VCXO circuit requires an external pullable
crystal for operation. External loop filter components enable
a PLL configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK1581-01 is configured to generate either a 1.544
MHz T1 clock or a 2.048 MHz E1 clock from an 8 kHz input
clock. Please refer to the Output Clock Selection Table on
Page 2. Input bit SEL is set according to this table, as is the
external crystal frequency. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK1581-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK1581-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK1581-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK1581-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK1581-01 and the crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
A list of approved crystals is located on the IDT web site
(www.idt.com).
PLL Loop Filter Components
A phased-locked loop (PLL) is a control system that keeps
the VCO frequency and phase locked with the input
reference clock. Like all control systems, analog PLL circuits
use a loop filter to establish operating stability. The
MK1581-01 uses external loop filter components for the
following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components RS,
CS and CP. RSET establishes PLL charge pump current and
therefore influences loop filter characteristics.
Design aid tools for configuring the loop filter can be found
at www.idt.com, including on-line and PC-based calculators.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1581-01GILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1581-01GITR | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK159 | 制造商:Velleman Inc 功能描述:Brain Game Kit |
| MK15-B-0 | 制造商:MEDER 制造商全稱:Meder Electronic 功能描述:MK Reed Sensors |
| MK15-B-0_DE | 制造商:MEDER 制造商全稱:Meder Electronic 功能描述:(deutsch) MK Reed Sensor |
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