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參數(shù)資料
| 型號(hào)： | MJ1001 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| 封裝： | METAL, TO-3, 2 PIN |
| 文件頁數(shù)： | 9/59頁 |
| 文件大小： | 361K |
| 代理商： | MJ1001 |
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Surface Mount Package Information and Tape and Reel Specifications
4–2
Motorola Bipolar Power Transistor Device Data
INFORMATION FOR USING SURFACE MOUNT PACKAGES
RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection inter-
face between the board and the package. With the correct
pad geometry, the packages will self align when subjected to
a solder reflow process.
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For example,
for a D2PAK, PD is calculated as follows.
PD =
150
°C – 25°C
50
°C/W
= 2.5 watts
The 50
°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain/collector pad. By increasing the area of the drain/
collector pad, the power dissipation can be increased.
Although the power dissipation can almost be doubled with
this method, area is taken up on the printed circuit board
which can defeat the purpose of using surface mount
technology. For example, a graph of R
θJA versus drain pad
area is shown in Figures 1 and 2.
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
DPAK
0.19
0
4.82
6
mm
inches
0.10
0
2.54
0.063
1.6
0.165
4.191
0.118
3.0
0.243
6.172
D2PAK
mm
inches
0.33
8.38
0.08
2.032
0.04
1.016
0.63
17.02
0.42
10.6
6
0.1
2
3.0
5
0.24
6.096
1.75 Watts
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25°C
A, AREA (SQUARE INCHES)
T
O
AMBIENT
(
C/W)°
R
JA
,T
HERM
AL
RESIS
TA
NCE,
JUNC
T
ION
θ
Figure 1. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
Figure 2. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
2.5 Watts
A, AREA (SQUARE INCHES)
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
TA = 25°C
60
70
50
40
30
20
16
14
12
10
8
6
4
2
0
3.5 Watts
5 Watts
T
O
AMBIENT
(
C/W)°
R
JA
,T
HERM
AL
RESIS
TA
NCE,
JUNC
T
ION
θ
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MJ10012 | 制造商:NTE Electronics 功能描述:NPN Silicon Power Darlington Transistor, 400 Volts, 175 Watts, 10 A 制造商:ON Semiconductor 功能描述:Trans Darlington NPN 400V 10A 3-Pin(2+Tab) TO-204AA 制造商:NTE Electronics 功能描述:TRANSISTOR 制造商:SPC Multicomp 功能描述:TRANSISTOR DARLINGTON TO-3 制造商:NTE Electronics 功能描述:BIPOLAR TRANSISTOR, NPN, 8V, TO-3; Transistor Polarity:NPN; Collector Emitter Voltage V(br)ceo:8V; Power Dissipation Pd:175W; DC Collector Current:10A; DC Current Gain hFE:300; Operating Temperature Min:-65C; No. of Pins:2 ;RoHS Compliant: Yes |
| MJ10012 | 制造商:NTE Electronics 功能描述:BIPOLAR TRANSISTOR |
| MJ10013 | 制造商:MOSPEC 制造商全稱:Mospec Semiconductor 功能描述:POWER TRANSISTORS(10A,550-600V,175W) |
| MJ10014 | 制造商:undefined 功能描述: |
| MJ10015 | 制造商:Solid State Devices Inc (SSDI) 功能描述:TRANSISTOR DARLING NPN 400V TO-3 制造商:SOLID STATE 功能描述:TRANSISTOR, DARLING, NPN, 400V, TO-3 制造商:Solid State Devices Inc (SSDI) 功能描述:DARLINGTON TRANSISTOR, NPN, 400V, TO-3; Transistor Polarity:NPN; Collector Emitter Voltage V(br)ceo:400V; Power Dissipation Pd:250W; DC Collector Current:-30A; DC Current Gain hFE:1000; Operating Temperature Min:-65C; No. of Pins:2 ;RoHS Compliant: Yes |
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