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| 型號： | MF6 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 6th Order Switched Capacitor Butterworth Lowpass |
| 中文描述： | 6階巴特沃斯低通開關(guān)電容 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 878K |
| 代理商： | MF6 |
2.0 Designing with the MF6
(Continued)
2.5 ALIASING CONSIDERATIONS
Aliasing effects have to be taken into consideration when in-
put signal frequencies exceed half the sampling rate. For the
MF6 this equals half the clock frequency (f
). When the in-
put signal contains a component at a frequency higher than
half the clock frequency, as in Figure 19a that component
will be “reflected” about f
/2 into the frequency range be-
low f
CLK
/2 as in Figure 19b If this component is within the
passband of the filter and of large enough amplitude it can
cause problems. Therefore if frequency components in the
input signal exceed f
/2 they must be attenuated before
being applied to the MF6 input. The necessary amount of at-
tenuation will vary depending on system requirements. In
critical applications the signal components above f
/2 will
have to be attenuated at least to the filter’s residual noise
level. An example circuit is shown in Figure 20 using one of
the uncommitted Op-Amps available in the MF6.
DS005065-30
f
IN
= 1.5 kHz (scope time base = 2 ms/div)
FIGURE 17. MF6-50 Abrupt Clock Frequency Change
DS005065-31
FIGURE 18. MF6-50 Step Input Response, Vertical =
2V/div., Horizontal = 1 ms/div., f
CLK
= 100 kHz
DS005065-37
(a) Input Signal Spectrum
DS005065-38
(b) Output Signal Spectrum. Note that the input signal
at f
s
/2 + f causes an output signal to appear at f
s
/2 f.
FIGURE 19. The phenomenon of aliasing in sampled-data systems. An input signal whose frequecy is greater than
one-half the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling
frequency. In the MF6, f
s
f
CLK
.
www.national.com
18
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