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參數(shù)資料
| 型號： | MESC-PM3 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller， Performance Monitor -127 Connections(可執(zhí)行檢測127個連接的增強型服務控制器) |
| 中文描述： | 增強服務控制器，性能監(jiān)視器-127連接（可執(zhí)行檢測127個連接的增強型服務控制器） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MESC-PM3 |
August 2000
MESC_PM3
MACRO
Data Sheet
Logic Design Solutions
4/15
1.3
Pin Description
Signal
CK50
RESETN
Direction
Input
Input
Activity
R edge
Low
Description
FPGA system clock. Must be connected to APC ESCLK signal.
FPGA system asynchronous reset.
CSN
RWN
Input
Input
Input
Low
-
High
FPGA chip select.
FPGA read write. 1 => Read. 0 => Write.
FPGA address lines.
ADDRESS(10:0
)
DATA(31:0)
Input/outpu
t
output
output
High
FPGA data lines. Active high.
RDYN
IRQN
Low /ts
Low
FPGA acknowledges write or read data. In three state when not active.
FPGA interruption in case of overflow. Active low during 80ns.
ESC_SYNC
ESC_TXD(15:0)
Input
Input
High
High
FPGA synchronisation pulse. Must be connected to APC ESSYNC signal.
FPGA ESC data. Must be connected to APC ESTXD signal.
1.4
Functionnal Description
The MESC_PM3 Controller is composed of two main functions.
The first function is a Connection Memory which contains the CPU programmed connection to be monitored. Up to 127
connection can be monitored.
The second function contains six statistic counters for up to 127 connections.
When the connection on the E.S.I. bus is programmed as to be active in the Connection Memory, the six statistic counters of
this connection are updated according E.S.I. data.
If one statistic counter roll over, one interruption is generated and one status interrupt register is updated to inform the CPU.
When the CPU reads the statistic counters of a paricular channel, this will reset all the statistic counters associated to this
connection.
Connection
Memory
127
Connections
E.S.I. bus
CPU_Write
127 Connections
Stat. 0
Stat. A
Stat. B
Stat. C
Stat. E
Stat. F
CPU_Read
Irq_ovf
Block Size
Add
Active
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