
August 2000
MESC_PM3
MACRO
Data Sheet
Logic Design Solutions
2/15
1.
Description................................................................................................................................................................................................3
1.1
Implementation example....................................................................................................................................................................3
1.2
Symbol...................................................................................................................................................................................................3
1.3
Pin Description...................................................................................................................................................................................4
1.4
Functionnal Description....................................................................................................................................................................4
1.5
E.S.I. interface.....................................................................................................................................................................................5
1.6
Performance Monitor Register........................................................................................................................................................6
1.6.1
Register Address Map.............................................................................................................................................................6
1.6.2
Registers.....................................................................................................................................................................................6
1.6.2.1
Connection memory ............................................................................................................................................................6
1.6.2.2
Error Threshold Divider Register......................................................................................................................................7
1.6.2.3
Lost Threshold Divider Register.......................................................................................................................................7
1.6.2.4
Misinserted Threshold Divider Register..........................................................................................................................9
1.6.2.5
Channel Counter Read Request Register.......................................................................................................................10
1.6.2.6
Stat. 0 read register............................................................................................................................................................10
1.6.2.7
Stat. A read register...........................................................................................................................................................10
1.6.2.8
Stat. B read register...........................................................................................................................................................11
1.6.2.9
Stat. C read register...........................................................................................................................................................11
1.6.2.10
Stat. E read register......................................................................................................................................................11
1.6.2.11
Stat. F read register......................................................................................................................................................12
1.6.2.12
Status Interupt register................................................................................................................................................12
1.7
Write cycle........................................................................................................................................................................................13
1.8
Read cycle..........................................................................................................................................................................................13
1.9
FPGA Timing....................................................................................................................................................................................13
1.10
Pin-Out.........................................................................................................................................................................................14
1.11
FPGA Configuration..................................................................................................................................................................15
2.
Customization........................................................................................................................................................................................16
2.1
CPU Interface...................................................................................................................................................................................16
2.2
New statistics definition.................................................................................................................................................................16
2.3
FPGA package..................................................................................................................................................................................16
3.
Tool version used...................................................................................................................................................................................16
4.
Recommended Design Experience.....................................................................................................................................................16
5.
Available Support Products.................................................................................................................................................................16
6.
Ordering Information...........................................................................................................................................................................16
7.
Related Information..............................................................................................................................................................................16