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參數(shù)資料
| 型號： | MESC-PM3 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller， Performance Monitor -127 Connections(可執(zhí)行檢測127個連接的增強型服務控制器) |
| 中文描述： | 增強服務控制器，性能監(jiān)視器-127連接（可執(zhí)行檢測127個連接的增強型服務控制器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MESC-PM3 |
August 2000
MESC_PM3
MACRO
Data Sheet
Logic Design Solutions
10/15
1.6.2.5
Channel Counter Read Request Register
Address = 20C\h.
Read Write.
To read the counters (Stat.0, A, B, C, E, F) of a particular Connection, the CPU has to set one Read and Reset Request bit to one
and write also in the same time the particular Connection number. When the Read and Reset Request bit is reset by the FPGA,
then the CPU can read the counter values associated with the Connection number programmed.
The Connection number corresponds to the Connection Memory Address, i.e. Connection 1 corresponds to Connection
Memory address 004\h.
BIT
6..0
DESCRIPTION
Connection Number :
00\h : Unused
01\h : Connection 1
…
7E\h : Connection 126
7F\h : Connection 127
Read and Reset Request Bit (Stat.0, A, B, C, E, F)
1 : Execute instruction.
0 : Instruction done.
Mask Interruption bit. 0 => masked / 1 => not masked.
Not used.
7
8
31:9
1.6.2.6
Stat. 0 read register.
Address = 400\h.
Read only.
24-bits Counter.
Ingress Received Cell Blocks (for convenience called - Stat 0)
This counter counts the number of blocks received since the last CPU read.
One CPU read will reset this counter.
BIT
23..0
31:24
DESCRIPTION
Stat. 0 read register
Not used.
1.6.2.7
Stat. A read register.
Address = 404\h.
Read only.
16-bits Counter.
Ingress Severely Errored Cell Blocks. This statistic is listed in Bellcore GR1248-CORE 11/98 Section 7.1.3.2.1, called Stat A.
One CPU read will reset this counter.
BIT
15..0
31:16
DESCRIPTION
Stat. A read register
Not used.
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