參數(shù)資料
型號: MESC-PM1
廠商: Lineage Power
英文描述: Enhanced Services Controller, Performance Monitor - 127 Connections(可執(zhí)行檢測127個連接的增強型服務控制器)
中文描述: 增強服務控制器,性能監(jiān)視器- 127連接(可執(zhí)行檢測127個連接的增強型服務控制器)
文件頁數(shù): 4/15頁
文件大?。?/td> 503K
代理商: MESC-PM1
April 2000
MESC_PM1
MACRO
Data Sheet
Logic Design Solutions
4/14
1.3
Pin Description
Signal
CK50
RESETN
Direction
Input
Input
Activity
R edge
Low
Description
FPGA system clock. Must be connected to APC ESCLK signal.
FPGA system asynchronous reset.
CSN
RWN
Input
Input
Input
Low
-
High
High
Low /ts
Low
FPGA chip select.
FPGA read write. 1 => Read. 0 => Write.
FPGA address lines.
FPGA data lines. Active high.
FPGA acknowledges write or read data. In three state when not active.
FPGA interruption in case of overflow. Active low during 80ns.
ADDRESS(10:0)
DATA(31:0)
RDYN
IRQN
Input/output
output
output
ESC_SYNC
ESC_TXD(15:0)
Input
Input
High
High
FPGA synchronisation pulse. Must be connected to APC ESSYNC signal.
FPGA ESC data. Must be connected to APC ESTXD signal.
1.4
Functionnal Description
The MESC_PM1 Controller is composed of two main functions.
The first function is a Connection Memory which contains the CPU programmed channel to be monitored. Up to 127
channels can be monitored among the 64k possible connections supported within the APC itself.
The second function contains seven statistic counters for up to 127 channels.
When one match happen between the E.S.I. bus and the Connection Memory on a particular channel, the seven statistic
counters of this channel are updated according E.S.I. data.
If one statistic counter roll over, one interruption is generated and one status interrupt register is updated to inform the CPU.
When the CPU reads the statistic counters of a paricular channel, this will reset all the statistic counters associated to this
channel (except for Stat.1 which has a specific reset mechanism).
Connection
Memory
127 Channels
E.S.I. bus
CPU_Write
127 Channels
Stat. 0
Stat. 1
Stat. A
Stat. B
Stat. C
Stat. E
Stat. F
CPU_Read
Irq_ovf
Match
Add
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