參數(shù)資料
型號： MESC-PM1
廠商： Lineage Power
英文描述： Enhanced Services Controller， Performance Monitor - 127 Connections(可執(zhí)行檢測127個(gè)連接的增強(qiáng)型服務(wù)控制器)
中文描述： 增強(qiáng)服務(wù)控制器，性能監(jiān)視器- 127連接（可執(zhí)行檢測127個(gè)連接的增強(qiáng)型服務(wù)控制器）
文件頁數(shù)： 2/15頁
文件大?。?/td> 503K
代理商： MESC-PM1
April 2000
MESC_PM1
MACRO
Data Sheet
Logic Design Solutions
2/14
1.
Description......................................................................................................................................3
1.1
Implementation example..........................................................................................................................3
1.2
Symbol .....................................................................................................................................................3
1.3
Pin Description.........................................................................................................................................4
1.4
Functionnal Description...........................................................................................................................4
1.5
E.S.I. interface .........................................................................................................................................5
1.6
Performance Monitor Register................................................................................................................6
1.6.1
Register Address Map .....................................................................................................................................6
1.6.2
Registers .........................................................................................................................................................6
1.6.2.1 Connection memory....................................................................................................................................6
1.6.2.2 Error Threshold Divider Register................................................................................................................7
1.6.2.3 Lost Threshold Divider Register .................................................................................................................7
1.6.2.4 Misinserted Threshold Divider Register......................................................................................................9
1.6.2.5 Channel Counter Read Request Register...................................................................................................10
1.6.2.6 Stat. 1 read register...................................................................................................................................10
1.6.2.7 Stat. A read register..................................................................................................................................11
1.6.2.8 Stat. B read register. .................................................................................................................................11
1.6.2.9 Stat. C read register..................................................................................................................................11
1.6.2.10
Stat. E read register..............................................................................................................................12
1.6.2.11
Stat. F read register..............................................................................................................................12
1.6.2.12
Status Interupt register.........................................................................................................................12
1.6.2.13
Stat. 0 read register. .............................................................................................................................13
1.7
Write cycle.............................................................................................................................................13
1.8
Read cycle..............................................................................................................................................14
1.9
FPGA Timing.........................................................................................................................................14
2
.
Tool version used..........................................................................................................................15
3.
Recommended Design Experience................................................................................................15
4.
Available Support Products .........................................................................................................15
5.
Ordering Information...................................................................................................................15
6.
Related Information......................................................................................................................15
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