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參數(shù)資料
| 型號(hào)： | MESC-PM1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller， Performance Monitor - 127 Connections(可執(zhí)行檢測(cè)127個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| 中文描述： | 增強(qiáng)服務(wù)控制器，性能監(jiān)視器- 127連接（可執(zhí)行檢測(cè)127個(gè)連接的增強(qiáng)型服務(wù)控制器） |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 503K |
| 代理商： | MESC-PM1 |
April 2000
MESC_PM1
MACRO
Data Sheet
Logic Design Solutions
10/14
1.6.2.5
Channel Counter Read Request Register
Address = 20C\h.
Read Write.
To read the counters (Stat.0, A, B, C, E, F) of a particular channel, the CPU has to set one Read and Reset Request bit 0 to
one and write also in the same time the particular channel number. When the Read and Reset Request bit 0 is reset by the
FPGA, then the CPU can read the counter values associated with the channel number programmed.
The channel number corresponds to the Connection Memory Address, i.e. channel 1 corresponds to Connection Memory
address 004\h.
BIT
6..0
DESCRIPTION
Channel Number :
00\h : Unused
01\h : Channel 1
…
7E\h : Channel 126
7F\h : Channel 127
Read and Reset Request Bit 0 (Stat.0, A, B, C, E, F)
Read and Reset Request Bit 1 (Stat.1)
Mask Interruption bit. 0 => masked / 1 => not masked.
Not used.
7
8
9
31:10
The Statistic 1 is the Ingress Cells Received in Block count. This statistic is required internally to the MESC_PM1 for
synchronising the Total Transmitted Cell Counts (Stat.F) to the other PM parameters.
The Total Transmitted Cell Counts (Stat.F) is updated at the end of a PM block.
The Read and Reset Request Bit 1 enables the CPU to read and reset Ingress Cells Received in Block count for a particular
channel. This has to be done typically when deactivating a Channel in the connection memory (writing FFFF\h). The
possibility to read the Ingress Cells Received in Block count value (Stat.1) is only for debug purpose.
Both Read and Reset Request Bit 1 and 0 can be written in same time.
1.6.2.6
Stat. 1 read register.
Address = 400\h.
Read only.
24-bits Counter.
Ingress Received Cell Blocks (for convenience called - Stat 0)
This counter counts the number of blocks received since the last CPU read.
One CPU read will reset this counter.
BIT
23..0
31:24
DESCRIPTION
Stat. 0 read register
Not used.
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