
iii
AT90CAN128
4250E–CAN–12/04
Modes of Operation.......................................................................................... 121
Timer/Counter Timing Diagrams....................................................................... 128
16-bit Timer/Counter Register Description ........................................................131
8-bit Timer/Counter2 with PWM and Asynchronous Operation... 140
Features............................................................................................................ 140
Overview........................................................................................................... 140
Timer/Counter Clock Sources........................................................................... 142
Counter Unit...................................................................................................... 142
Output Compare Unit........................................................................................ 143
Compare Match Output Unit..............................................................................145
Modes of Operation.......................................................................................... 145
Timer/Counter Timing Diagrams........................................................................150
8-bit Timer/Counter Register Description ..........................................................151
Asynchronous operation of the Timer/Counter2............................................... 154
Timer/Counter2 Prescaler..................................................................................158
Output Compare Modulator - OCM ................................................. 160
Overview........................................................................................................... 160
Description........................................................................................................ 160
Serial Peripheral Interface – SPI...................................................... 162
Features............................................................................................................ 162
SS Pin Functionality...........................................................................................167
Data Modes .......................................................................................................170
USART (USART0 and USART1)....................................................... 171
Features............................................................................................................ 171
Dual USART..................................................................................................... 171
Overview........................................................................................................... 172
Clock Generation.............................................................................................. 173
Serial Frame..................................................................................................... 175
USART Initialization.......................................................................................... 176
Data Transmission – USART Transmitter .........................................................178
Data Reception – USART Receiver...................................................................180
Asynchronous Data Reception......................................................................... 184
Multi-processor Communication Mode..............................................................187
USART Register Description.............................................................................189
Examples of Baud Rate Setting........................................................................ 195
Two-wire Serial Interface ................................................................. 199
Features............................................................................................................ 199
Two-wire Serial Interface Bus Definition........................................................... 199
Data Transfer and Frame Format..................................................................... 200
Multi-master Bus Systems, Arbitration and Synchronization............................ 202
Overview of the TWI Module .............................................................................205