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參數(shù)資料
| 型號(hào)： | MCZ33880EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Configurable Octal Serial Switch with Serial Peripheral Interface I/O |
| 中文描述： | 配置八路系列開關(guān)串行外設(shè)接口的I / O |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 341K |
| 代理商： | MCZ33880EG |
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
33880
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
≤
V
DD
≤
5.25 V, 9.0 V
≤
V
PWR
≤
16 V, -40
°
C
≤
T
C
≤
125
°
C
unless otherwise
noted. Typical values, where applicable, reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25
°
C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate Low-Side Configuration
(12)
R
L
= 620
t
R
0.1
0.5
1.2
V/
μ
s
Output Slew Rate Low-Side Configuration
(12)
R
L
= 620
t
F
0.1
0.5
1.2
V/
μ
s
Output Slew Rate High-Side Configuration
(12)
R
L
= 620
t
R
0.1
0.3
1.2
V/
μ
s
Output Slew Rate High-Side Configuration
(12)
R
L
= 620
t
F
0.1
0.3
1.2
V/
μ
s
Output Turn ON Delay Time, High-Side and Low-Side Configuration
(13)
t
DLY(ON)
1.0
15
50
μ
s
Output Turn OFF Delay Time, High-Side and Low-Side Configuration
(13)
t
DLY(OFF)
1.0
30
100
μ
s
Output Fault Delay Time
(14)
t
FAULT
100
–
300
μ
s
DIGITAL INTERFACE TIMING
Recommended Frequency of SPI Operation
–
–
4.0
6.0
MHz
Required Low State Duration on V
DD
for Reset
(15)
V
DD
≤
0.2 V
t
RESET
–
4.0
10
μ
s
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t
LEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t
LAG
50
–
–
ns
DI to Falling Edge of SCLK (Required Setup Time)
t
DI(su)
16
–
–
ns
Falling Edge of SCLK to DI (Required Hold Time)
t
DI(HOLD)
20
–
–
ns
DI, CS, SCLK Signal Rise Time
(16)
t
R(DI)
–
5.0
–
ns
DI, CS, SCLK Signal Fall Time
(16)
t
F(DI)
–
5.0
–
ns
Time from Falling Edge of CS to DO Low Impedance
(17)
t
DO(EN)
–
–
60
ns
Time from Rising Edge of CS to DO High Impedance
(18)
t
DO(DIS)
–
–
60
ns
Time from Rising Edge of SCLK to DO Data Valid
(19)
t
VALID
–
25
60
ns
Notes
12.
13.
14.
15.
16.
17.
18.
19.
Output Rise and Fall time respectively measured across a 620
resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
Output turn ON and OFF delay time measured from 50 percent rising edge of
CS
to 90 and 10 percent of initial voltage.
Duration of fault before fault bit is set. Duration between access times must be greater than 300
μ
s to read faults.
This parameter is guaranteed by design but is not production tested.
Rise and Fall time of incoming DI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at DO pin.
Time required for output status data to be terminated at DO pin
Time required to obtain valid data out from DO following the rise of SCLK.
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