2002 Microchip Technology Inc.
DS21287F-page 7
MCRF355/360
2.0
FUNCTIONAL DESCRIPTION
The device contains three major sections: (1) Analog
Front-End, (2) Controller Logic and (3) Memory.
Figure 2-1 shows the block diagram of the device.
2.1
Analog Front-End Section
This section includes power supply, Power-on Reset,
and data modulation circuits.
2.1.1
POWER SUPPLY
The power supply circuit generates DC voltage (V
DD
)
by rectifying induced RF coil voltage. The power supply
circuit includes high-voltage clamping diodes to pre-
vent excessive voltage development across the
antenna coil.
2.1.2
POWER-ON-RESET (POR)
This circuit generates a Power-on Reset when the tag
first enters the reader field. The RESET releases when
sufficient power has developed on the V
DD
regulator to
allow for correct operation.
2.1.3
DATA MODULATION
The data modulation circuit consists of a modulation
transistor and an external LC resonant circuit. The
external circuit must be tuned to the carrier frequency
of the reader (i.e., 13.56 MHz) for maximum perfor-
mance.
The modulation transistor is placed between antenna B
and Vss pads and has small turn-on resistance (R
M
).
This small turn-on resistance shorts the external circuit
between the antenna B and Vss pads as it turns on.
The transistor turns on during the “Hi” period of the
modulation data and turns off during the “Lo” period.
When the transistor is turned off, the resonant circuit
resonates at the carrier frequency. Therefore, the
external circuit develops maximum voltage across it.
This condition is called uncloaking (tuned). When the
transistor is turned on, its low turn-on resistance shorts
the external circuit, and therefore the circuit no longer
resonates at the carrier frequency. The voltage across
the external circuit is minimized. This condition is called
cloaking (detuned).
The device transmits data by cloaking and uncloaking
based on the on/off condition of the modulation transis-
tor. Therefore, with the 70 kHz - Manchester format, the
data bit “0” will be sent by cloaking (detuned) and
uncloaking (tuned) the device for 7
μ
s each. Similarly,
the data bit “1” will be sent by uncloaking (tuned) and
cloaking (detuned) the device for 7
μ
s each. See
Figure 2-2 for the Manchester waveform.
FIGURE 2-1:
BLOCK DIAGRAM
SLEEP Timer
(anti-collision)
Modulation
Read/Write Logic
Test Logic
Column Drivers
(High Voltage Circuit)
Address
Set/Clear
Data
V
DD
Modulation
Pulse
CLK Pulse
Wake-up Signal
CONTROLLER LOGIC SECTION
Memory Array
V
PRG
and CLK
154-Bit
Power Supply
Column and Row Decoders
Clock Generator
Modulation Logic
Power-on Reset
POR
MEMORY SECTION
ANALOG FRONT-END SECTION