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參數(shù)資料
| 型號(hào)： | MCP6S26 |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | FPGA |
| 英文描述： | 400000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 單端，軌至軌I / O，低增益美國(guó)PGA |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 880K |
| 代理商： | MCP6S26 |
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2003 Microchip Technology Inc.
DS21117A-page 9
MCP6S21/2/6/8
2.0
TYPICAL PERFORMANCE CURVES
Note:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +5.0V, V
SS
= GND, V
REF
= V
SS
, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 k
to V
DD
/2, and C
L
= 60 pF.
FIGURE 2-1:
DC Gain Error, G = +1.
FIGURE 2-2:
DC Gain Error, G
≥
+2.
FIGURE 2-3:
Ladder Resistance Drift.
FIGURE 2-4:
DC Gain Drift, G = +1.
FIGURE 2-5:
DC Gain Drift, G
≥
+2.
FIGURE 2-6:
V
DD
= 4.0V.
Input Offset Voltage,
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-
-
-
-
-
-
-
-
-
-
0
0
DC Gain Error (%)
P
420 Samples
G = +1
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-
-
-
-
-
0
0
0
0
0
0
DC Gain Error (%)
P
420 Samples
G
t
+2
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
0
0
0
0
0
0
0
0
0
Ladder Resistance Drift (%/°C)
P
420 Samples
T
A
= -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-
-
-
-
-
-
0
0
0
0
0
0
0
DC Gain Drift (%/°C)
P
420 Samples
G = +1
T
A
= -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-
-
-
-
-
0
0
0
0
0
0
DC Gain Drift (%/°C)
P
420 Samples
G
t
+2
T
A
= -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-
-
-
-
-
-
0
4
8
1
1
2
2
Input Offset Voltage (μV)
P
360 Samples
V
DD
= 4.0 V
G = +1
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