fSCL 0— 3.4 1.7" />
參數(shù)資料
型號： MCP3421A0T-E/OT
廠商： Microchip Technology
文件頁數(shù)： 11/30頁
文件大小： 0K
描述： IC ADC 18BIT 3.75SPS 1CH SOT23-6
標準包裝： 1
位數(shù)： 18
采樣率（每秒）： 3.75
數(shù)據(jù)接口： I²C，串行
轉換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應商設備封裝： SOT-23-6
包裝： 標準包裝
輸入數(shù)目和類型： 2 個單端，雙極；1 個差分，單極
配用： MCP3421EV-ND - BOARD EVAL FOR MCP3421 SOT23-6
其它名稱： MCP3421A0T-E/OTDKR
2006 Microchip Technology Inc.
DS22003B-page 19
MCP3421
High Speed Mode
Clock frequency
fSCL
0—
3.4
1.7
MHz
Cb = 100 pF
Cb = 400 pF
Clock high time
THIGH
60
120
——
ns
Cb = 100 pF
Cb = 400 pF
Clock low time
TLOW
160
320
——
ns
Cb = 100 pF
Cb = 400 pF
SCL rise time (Note 1)
TR
——
40
80
ns
From VIL to VIH,Cb = 100 pF
Cb = 400 pF
SCL fall time (Note 1)
TF
——
40
80
ns
From VIH to VIL,Cb = 100 pF
Cb = 400 pF
SDA rise time (Note 1)
TR: DAT
——
80
160
ns
From VIL to VIH,Cb = 100 pF
Cb = 400 pF
SDA fall time (Note 1)
TF: DATA
——
80
160
ns
From VIH to VIL,Cb = 100 pF
Cb = 400 pF
START condition hold time
THD:STA
160
—
ns
After this period, the first clock
pulse is generated
Repeated START condition
setup time
TSU:STA
160
—
ns
Only relevant for repeated Start
condition
Data hold time (Note 4)
THD:DAT
0
—70
150
ns
Cb = 100 pF
Cb = 400 pF
Data input setup time
TSU:DAT
10
—
ns
STOP condition setup time
TSU:STO
160
—
ns
STOP condition hold time
THD:STD
160
—
ns
Output valid from clock
(Notes 2 and 3)
TAA
—
150
310
ns
Cb = 100 pF
Cb = 400 pF
Bus free time
TBUF
160
—
ns
Time between START and STOP
conditions.
Input filter spike suppression
TSP
0
—
10
ns
SDA and SCL pins
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V,
VSS = 0V, VIN+ = VIN- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5:
This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.
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