參數(shù)資料
型號(hào)： MCP2122T-E/SNG
廠商： Microchip Technology
文件頁(yè)數(shù)： 33/34頁(yè)
文件大小： 0K
描述： IC ENCODER/DECODR INFRARED 8SOIC
標(biāo)準(zhǔn)包裝： 3,300
類型： 紅外線編碼器/解碼器
應(yīng)用： 數(shù)據(jù)記錄，數(shù)據(jù)交換
電壓 - 電源，模擬： 1.8 V ~ 5.5 V
電壓 - 電源，數(shù)字： 1.8 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 帶卷 (TR)
配用： MCP212XDM-ND - BOARD DEVELOPMENT IRDA
其它名稱： MCP2122T-E/SNGR
MCP2122T-E/SNGR-ND
MCP2122
DS21894B-page 8
Preliminary
2004 Microchip Technology Inc.
2.4.1
BAUD RATE
The baud rate for the MCP2122 is determined by the
frequency of the 16XCLK signal. Equation 2-1
demonstrates how to calculate the 16XCLK frequency
based on the desired baud rate. Table 2-3 shows some
common baud rates and the corresponding 16XCLK
frequency.
EQUATION 2-1:
16XCLK FREQUENCY
TABLE 2-3:
COMMON BAUD RATE/
16XCLK FREQUENCY
2.5
Encoder/Decoder
The IR encoder/decoder is made up of two major
components. They are:
IR Decoder
IR Encoder
The encoder receives UART data (bit by bit) and
outputs a data bit in the IrDA standard bit format.
Figure 2-8 shows a functional block diagram of the
encoder.
The decoder receives IrDA standard data (bit by bit)
and outputs data in UART data bit format. Figure 2-8
shows a functional block diagram of the decoder.
The encoder/decoder has two interfaces. They are:
Host UART interface
IR interface
2.5.1
ENCODING (MODULATION)
Each bit time is comprised of 16 bit clocks. If the value
to be transmitted (as determined by the TX pin) is a
logic-low, the TXIR pin will output a low level for 7-bit
clock cycles, a logic-high level for 3-bit clock (with a
maximum high-time of about 4 s) cycles, with the
remaining time (6-bit clock cycles or more) being low. If
the value to transmit is a logic-high, the TXIR pin will
output a low level for the entire 16 bit clock cycle.
2.5.2
DECODING (DEMODULATION)
Each bit time is comprised of 16 bit clocks. If the value
to be received is a logic-low, the RXIR pin will be a low
level for the first 3-bit clock cycle (or a minimum of
1.6 s), with the remaining time (13-bit clock cycles)
being high. If the value to be received is a logic-high,
the RXIR pin will be a high level for the entire 16-bit
clock cycle. The level on the RX pin will be in the
appropriate state for an entire 16-bit clock cycle.
FIGURE 2-8:
MCP2122 RECEIVE DETECT TO ENCODER/DECODER BLOCK DIAGRAM
Baud
Rate
16XCLK
Frequency
(F16XCLK)
Comment
9600
153,600
19,200
307,200
38,400
614,400
57,600
921,600
115,200
1,843,200
F16XCLK
16 (Desired Baud Rate)
=
TXIR
Glitch
Filter
Decode
RX
RXIR
Pulse Width
Limiter
Encode
TX
The following table shows the state on the RESET pin and how this effects the operation of the TXIR pin.
RESET State
Comment
VIH
TXIR output encoded value of TX pin
VIL
TXIR is forced low
(~ 4 s)
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