參數(shù)資料
型號(hào)： MCP2122T-E/SNG
廠商： Microchip Technology
文件頁(yè)數(shù)： 32/34頁(yè)
文件大小： 0K
描述： IC ENCODER/DECODR INFRARED 8SOIC
標(biāo)準(zhǔn)包裝： 3,300
類型： 紅外線編碼器/解碼器
應(yīng)用： 數(shù)據(jù)記錄，數(shù)據(jù)交換
電壓 - 電源，模擬： 1.8 V ~ 5.5 V
電壓 - 電源，數(shù)字： 1.8 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 帶卷 (TR)
配用： MCP212XDM-ND - BOARD DEVELOPMENT IRDA
其它名稱： MCP2122T-E/SNGR
MCP2122T-E/SNGR-ND
2004 Microchip Technology Inc.
Preliminary
DS21894B-page 7
MCP2122
2.4
16XCLK (Bit Clock)
The MCP2122 requires an external clock source to
operate. The 16XCLK pin is the device clock input (see
Figure 2-5) and is independent of the host UART
interface or the IR interface. The 16XCLK determines
all timing during device operation. It is the edge of the
16XCLK pin that causes activity to occur.
The 16XCLK signal can also be referred to as a bit
clock (BITCLK). There are 16 BITCLKs for each bit
time. The BITCLKs are used for the generation of the
Start bit, the eight data bits and the Stop bit.
When the embedded system could be receiving IR
communication, the MCP2122 is required to have the
16XCLK signal clocking at the expected frequency,
with minimal variation in that frequency. Between data
bytes (Stop bit to Start bit), the 16XCLK frequency can
be changed. This may occur in systems where the Host
Controller is implementing one of the IrDA standard
application layer protocols (such as IrObex).
When the embedded system does not want to receive
IR communications, the 16XCLK clock can be disabled
(static). This will reduce the power consumption of the
system.
Figure 2-6 shows the relationship of the 16XCLK signal
to the RXIR input, which then determines the RX output
signal. Figure 2-7 shows the relationship of the
16XCLK signal to the TX input, which then determines
the TXIR output signal. For device timing information,
FIGURE 2-5:
DEVICE CLOCK SOURCE
FIGURE 2-6:
16XCLK AND RX/RXIR
FIGURE 2-7:
16XCLK AND TX/TXIR
MCP2122
16XCLK
RXIR
RX
16 16XCLK
≤ 3 CLK
16 16XCLK
Bit A
Bit B
(input)
(output)
(input)
3 CLK (
≤ ~ 4 s)
16XCLK
TX
TXIR
16 16XCLK
Bit A
Bit B
(input)
(output)
(input)
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