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參數(shù)資料
| 型號： | MCM69R820C |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲(chǔ)器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 301K |
| 代理商： | MCM69R820C |
MCM69R738C
MCM69R820C
14
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture.
The TAP controller is the state machine that controls the TAP
operation and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE
1149.1 compliant TAPs. The TAP operates using conven-
tional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS
logic level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to VDD through a 1 k resistor. TDO should be left uncon-
nected.
TAP DC OPERATING CHARACTERISTICS
(VDD = 3.3 V
±
5%, 0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Notes
Logic Input Logic High
VIH1
VIL1
Ilkg
VOL1
VOH1
VOL2
VOH2
2.0
VDD + 0.3
0.8
V
Logic Input Logic Low
–0.3
V
Logic Input Leakage Current
—
±
5
μ
A
1
CMOS Output Logic Low
—
0.2
V
2
CMOS Output Logic High
VDD – 0.2
—
—
V
3
TTL Output Logic Low
0.4
V
4
TTL Output Logic High
2.4
—
V
5
NOTES:
1. 0 V
≤
Vin
≤
VDDQ for all logic input pins.
2. IOL1
≤
100
μ
A @ VOL = 0.2 V. Sampled, not 100% tested.
3. |IOH1|
≤
100
μ
A @ VDDQ – 0.2 V. Sampled, not 100% tested.
4. IOL2
≤
8 mA @ VOL = 0.4 V.
5. |IOH2|
≤
8 mA @ VOH = 2.4 V.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R820CZP4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R820CZP4.4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R820CZP4.4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R820CZP4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R820CZP5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
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