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參數(shù)資料
| 型號： | MCM69R819A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MCM69R819A |
MCM69R736C
MCM69R818C
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, 0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Max
–4
Max
–4.4
Max
–5
Max
–6
Max
Unit
Notes
Core Power Supply Voltage
VDD
VDDQ
IDD1
3.15
—
—
—
—
3.6
V
Output Driver Supply Voltage
1.4
—
—
—
—
1.9
V
Active Power Supply Current
(Device Selected, All Outputs Open,
Freq = Max, VDD = Max, VDDQ = Max).
Includes Supply Currents for VDD.
Quiescent Active Power Supply Current
(Device Selected, All Outputs Open,
Freq = 0, VDD = Max, VDDQ = Max).
Includes supply currents for VDD.
Active Standby Power Supply Current
(Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max)
—
795
775
750
750
—
mA
5
IDD2
—
540
540
540
540
—
mA
6
ISB1
—
400
400
400
400
—
mA
7
CMOS Standby Supply Current
(Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs
Static at CMOS Levels)
ISB2
—
390
390
390
390
—
mA
6, 7
Sleep Mode Current (ZZ = VIH,
Freq = Max, VDD = Max, VDDQ = Max)
IZZ
—
100
100
100
100
—
mA
6
Input Reference DC Voltage
Vref (dc)
0.6
—
—
—
—
1.1
V
8
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS
bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. 50% read and 50% write; all addresses switching.
6. CMOS levels for I/Os are VIC
≤
VSS + 0.2 V or
≥
VDDQ – 0.2 V. CMOS levels for other inputs are Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V.
7. Device deselected as defined by the Truth Table.
8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-
nent superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg(I)
Vin (dc)
VDIF (dc)
VCM (dc)
Vref + 0.1
–0.3
VDD + 0.3
Vref – 0.1
±
5
V
DC Input Logic Low
V
1
Input Leakage Current
—
μ
A
2
Clock Input Signal Voltage
–0.3
VDD + 0.3
VDD + 0.6
1.1
V
Clock Input Differential Voltage (See Figure 3)
0.2
V
3
Clock Input Common Mode Voltage Range (See Figure 3)
NOTES:
1. Inputs may undershoot to –1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See FIgure 2.
2. 0 V
≤
Vin
≤
VDD for all pins.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
0.6
V
4
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