參數(shù)資料
型號(hào)： MCM69R819A
廠商： Motorola, Inc.
英文描述： 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫(xiě)、快速靜態(tài)RAM)
中文描述： 4分位同步后寫(xiě)入快速靜態(tài)存儲(chǔ)器（4分位同步遲寫(xiě)，快速靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 309K
代理商： MCM69R819A
MCM69R736C
MCM69R818C
13
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
the output register and available at the outputs at tKHQV.
During this same cycle a new read address can be applied to
the address pins.
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers after the next rising edge of the CK clock.
SW low deselects the output drivers immediately (on the
same cycle). Output drive is also controlled directly by output
enable, G. No clock edges are required to generate output
disable with G. G asynchronously enables the output drivers.
Output data will be valid the latter of tGLQV and tKHQV.
Outputs will begin driving at tKHQX1. Outputs will hold pre-
vious data until tKHQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW)
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active, is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, a 250
resistor will give an out-
put impedance of 50
.
Impedance updates occur continuously and the frequency
of the update is based on the subdivided CK clock. Note that
if the CK clock stops so does the impedance update.
The actual change in the impedance occurs in small incre-
ments and is monotonic. There are no significant distur-
bances that occur on the output because of this smooth
update method.
The impedance update is not related to any particular type
of cycle because the impedance is updated continuously and
is based on the CK clock. Updates occur regardless of
whether the device is performing a read, write, or a deselect
cycle and does not depend on the state of G.
At power up or recovery from sleep mode, the output
impedance defaults to approximately 50
. It will take 4,000
to 16,000 cycles for the impedance to be completely updated
if the programmed impedance is much higher or lower than
50
.
The output buffers can also be programmed in a minimum
impedance configuration by connecting ZQ to VDD.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is rec-
ommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed
VDD + 0.5 V, whatever the instantaneous value of
VDD. Once supplies have reached specification levels, a
minimum dwell of 1.0 ms with CK clock inputs cycling is
required before beginning normal operations. At power up the
output impedance will be set at approximately 50
as stated
above.
相關(guān)PDF資料
PDF描述
MCM69R820AZP6 4M Late Write 2.5 V I/O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCM69R819AZP5 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:4M Late Write LVTTL
MCM69R819AZP5R 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:4M Late Write LVTTL
MCM69R819AZP6 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:4M Late Write LVTTL
MCM69R819AZP6R 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:4M Late Write LVTTL
MCM69R819AZP7 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:4M Late Write LVTTL
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