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參數(shù)資料
| 型號： | MCM69R819A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MCM69R819A |
MCM69R736C
MCM69R818C
1
MOTOROLA FAST SRAM
Motorola, Inc. 1999
4M Late Write HSTL
The MCM69R736C/818C is a 4M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R818C
(organized as 256K words by 18 bits) and the MCM69R736C (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control sig-
nals. Read data is also driven on the rising edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point
(Vref) and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or
the entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Byte Write Control
Single 3.3 V +10%, –5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69R736C/818C–4 = 4 ns
MCM69R736C/818C–4.4 = 4.4 ns
MCM69R736C/818C–5 = 5 ns
MCM69R736C/818C–6 = 6 ns
Sleep Mode Operation (ZZ pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
Order this document
by MCM69R736C/D
SEMICONDUCTOR TECHNICAL DATA
MCM69R736C
MCM69R818C
ZP PACKAGE
PBGA
CASE 999–02
REV 1
8/10/99
相關(guān)PDF資料 |
PDF描述 |
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| MCM69R820AZP6 | 4M Late Write 2.5 V I/O |
| MCM69R738AZP5 | 4M Late Write 2.5 V I/O |
| MCM69R820AZP5 | 4M Late Write 2.5 V I/O |
| MCM69R738AZP5R | 4M Late Write 2.5 V I/O |
| MCM69R820AZP5R | 4M Late Write 2.5 V I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R819AZP5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69R819AZP5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69R819AZP6 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69R819AZP6R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
| MCM69R819AZP7 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4M Late Write LVTTL |
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