MCM67Q909
3
MOTOROLA FAST SRAM
TRUTH TABLE
E
(tn)
W
(tn)
G
(tn+1
)
Mode
D0 – D8
(tn)
Q0 – Q8
(tn+1)
VCC
Current
L
L
L
Write and
Pass–Through
Valid
D0 – D8 (tn)
ICC
H
Write
Valid
High–Z
ICC
ICC
ICC
ICC
ICC
H
L
L
Pass–Through
Valid
D0 – D8 (tn)
High–Z
H
Pass–Through
Don’t Care
X
H
L
Read
Don’t Care
Qout (tn)
High–Z
H
Read
Don’t Care
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
Vin, Vout
–0.5 to 7.0
V
Voltage Relative to VSS for Any Pin
Except VCC
–0.5 to VCC + 0.5
V
Output Current
Iout
PD
Tbias
TA
Tstg
±
30
mA
Power Dissipation
1.7
W
Temperature Under Bias
–10 to 85
°
C
Operating Temperature
0 to 70
°
C
Storage Temperature — Plastic
–55 to 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS
(See Note 1)
Rating
Symbol
Max
Unit
Notes
Junction to Ambient Thermal Resistance
R
θ
JA or
θ
JA
R
θ
JC or
θ
JC
Ψ
JT
31.7
°
C/W
°
C/W
°
C/W
2
Junction to Case Thermal Resistance
6.8
3
Thermal Characterization Parameter
2.2
4
NOTES:
1. All values are determined using a single–layer thermal test board.
2. Junction to ambient thermal resistance is based on measurements on a horizontal single–sided printed circuit board per SEMI G38–87 and
EIA/JESD 51–6 with a 400 ft/min air flow.
3. Junction to case thermal resistance is based on measurements using a cold plate per MIL–STD 883D, Method 1012.1 and SEMI G30–88
with the exception that the cold plate temperature is used for the case temperature.
4. Thermal characterization parameter,
Ψ
JT, is defined in EIA/JESD 51–2. It is a measure of the difference in temperature between the junction
and a thermocouple on top of the package, normalized by the power dissipation with a 400 ft/min air flow.
This is a synchronous device. All synchro-
nous inputs must meet specified setup and hold
times with stable logic levels for
ALL
rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.