參數(shù)資料
型號: MCM63R736
廠商: Motorola, Inc.
英文描述: 4MBit Synchronous Late Write Fast Static RAM(4M位同步遲寫快速靜態(tài)RAM)
中文描述: 晚寫的4Mb同步快速靜態(tài)存儲器(4分位同步遲寫快速靜態(tài)內(nèi)存)
文件頁數(shù): 9/21頁
文件大?。?/td> 311K
代理商: MCM63R736
MCM63R736
MCM63R818
9
MOTOROLA FAST SRAM
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time is shown as a minimum since
the system must supply at least that much time. On the
other hand, responses from the memory are specified
from the device point of view. Thus, the access time is
shown as a maximum since the device never provides
data later than that time.
TIMING LIMITS
DEVICE
UNDER
TEST
ZQ
50
50
0.75 V
VDDQ/2
Vref
250
Figure 1. Test Loads
50
50
0.75 V
0.75 V
50
50
5 pF
5 pF
16.7
DQ
16.7
16.7
0.75 V
a. Test Load
b. Test Load
AC INPUT CHARACTERISTICS
(See Note 1)
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 4)
VIH (ac)
Vref + 200 mV
AC Input Logic Low (See Figures 2 and 4)
VIL (ac)
Vref – 200 mV
2
Input Reference Peak–to–Peak AC Voltage
Vref (ac)
5% Vref (dc)
3
Clock Input Differential Voltage
Vdif (ac)
400 mV
VDDQ + 500 mV
4
NOTES:
1. Inputs may overshoot to VDDQ + 1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See Figure 2.
2. Inputs may undershoot to –1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See Figure 2.
3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac compo-
nent superimposed on Vref may not exceed 5% of the dc component of Vref.
4. Minimum instantaneous differential input voltage required for differential input clock operation.
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