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參數(shù)資料
| 型號(hào)： | MCM63R836A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 8MBit快速同步后寫入靜態(tài)存儲(chǔ)器（800萬位同步遲寫快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 427K |
| 代理商： | MCM63R836A |
MCM63R836A
MCM63R918A
1
MOTOROLA FAST SRAM
Motorola, Inc. 1999
Advance Information
8M Late Write HSTL
The MCM63R836A/918A is an 8M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM63R918A
(organized as 512K words by 18 bits) and the MCM63R836A (organized as
256K words by 36 bits) are fabricated in Motorola’s high performance silicon gate
copper CMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is also driven on the rising edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or
the entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Byte Write Control
2.5 V – 5% to 3.3 V + 10% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM63R836A/918A–3.0 = 3.0 ns
MCM63R836A/918A–3.3 = 3.3 ns
MCM63R836A/918A–3.7 = 3.7 ns
MCM63R836A/918A–4.0 = 4.0 ns
MCM63R836A/918A–4.4 = 4.4 ns
Sleep Mode Operation (ZZ pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic
Ball Grid Array (PBGA)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM63R836A/D
SEMICONDUCTOR TECHNICAL DATA
MCM63R836A
MCM63R918A
FC PACKAGE
PBGA
CASE 999D–01
8/5/99
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM63R836FC3.0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.0R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.3R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
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