Interface to a TV Encoder," />
參數(shù)資料
型號(hào)： MCIMX31VKN5BR2
廠商： Freescale Semiconductor
文件頁數(shù)： 87/122頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31 457-MAPBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲(chǔ)器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 457-LFBGA
包裝： 帶卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
67
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
4.3.15.5
Asynchronous Interfaces
4.3.15.5.1
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when
the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type
1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer
direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals
(system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole
burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52,
Figure 53, Figure 54, and Figure 55. These timing images correspond to active-low DISPB_D#_CS,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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參數(shù)描述
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