參數(shù)資料
型號： MCIMX31VKN5BR2
廠商： Freescale Semiconductor
文件頁數(shù)： 29/122頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31 457-MAPBGA
標準包裝： 1,000
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 457-LFBGA
包裝： 帶卷 (TR)
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
14
Freescale Semiconductor
Electrical Characteristics
Table 10 provides information for interface frequency limits. For more details about clocks characteristics,
Table 11 shows the fusebox supply current parameters.
7 Supply voltage is considered “overdrive” for voltages above 3.1 V. Operation time in overdrive—whether switching or
not—must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without
significant device degradation—for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated
equipment. Operation at 3.3 V that exceeds a cumulative 3,504 hours may cause non-operation whenever supply voltage is
reduced to 1.8 V; degradation may render the device too slow or inoperable. Below 3.1 V, duty cycle restrictions may apply for
equipment rated above 5 years.
8 For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL
≥ Core – 100 mV. In other
words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. This restriction is no longer necessary on mask
set M91E. PLL supplies may be set independently of core supply. PLL voltage must not be altered after power up, otherwise
the PLL will be unstable and lose lock. To minimize inducing noise on the PLL supply line, source the voltage from a low-noise,
dedicated supply. PLL parameters in Table 31, "DPLL Specifications," on page 37, are guaranteed over the entire specified
voltage range.
9 Fusebox read supply voltage applies to silicon Revisions 1.2 and previous.
10 In read mode, FUSE_VDD can be floated or grounded for mask set M91E (silicon Revision 2.0).
11 Fuses might be inadvertently blown if written to while the voltage is below this minimum.
12 The temperature range given is for the consumer version. Please refer to Table 1 for extended temperature range offerings
and the associated part numbers.
Table 9. Specific Operating Ranges for Silicon Revision 2.0
Symbol
Parameter
Min
Max
Units
FUSE_VDD
Fusebox read Supply Voltage1
1 In read mode, FUSE_VDD should be floated or grounded.
——
V
Fusebox write (program) Supply Voltage2
2 Fuses might be inadvertently blown if written to while the voltage is below the minimum.
3.0
3.3
V
Table 10. Interface Frequency
ID
Parameter
Symbol
Min
Typ
Max
Units
1
JTAG TCK Frequency
fJTAG
DC
5
10
MHz
2
CKIL Frequency1
1 CKIL must be driven by an external clock source to ensure proper start-up and operation of the device. CKIL is needed to clock
the internal reset synchronizer, the watchdog, and the real-time clock.
fCKIL
32
32.768
38.4
kHz
3
CKIH Frequency2
2 DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication,
standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency
requires an update to the OS. For more details, refer to the particular OS user's guide documentation.
fCKIH
15
26
75
MHz
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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