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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
111
3.7.18.2
ADC Timing Diagrams
Figure 82 represents the synchronization between the signals clk, soc, eoc, and the output bits in the usage
of the internal ADC. After a conversion cycle eoc is asserted, a new conversion begins only when the
Power-down current
NVCC_ADC
QVDD
鈥斺€�
鈥�
1
10
uA
Touchscreen Interface
Expected plate resistance
鈥�
100
鈥�
1500
Switch drivers on resistance
GND and VDD switches
鈥�
10
Conversion Characteristics3
DNL4
fin = 1 kHz
鈥�
+/鈥�0.75
鈥�
LSB
INL4
fin = 1 kHz
鈥�
+/鈥�2.0
鈥�
LSB
Gain + Offset Error
鈥�
+/鈥�2
%FS
1 This comprises only the required initial dummy conversion cycle. Additional power-up time depends on the enadc, reset and
soc signals applied to the touchscreen controller.
2 This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the
touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA.
3 At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 掳C, fclk = 1.75 MHz, any process corner, unless otherwise noted.
4 Value measured with a 鈥�0.5 dBFS sinusoidal input signal and computed with the code density test.
Table 85. Touchscreen ADC Electrical Specifications (continued)
Parameter
Conditions
Min.
Typ.
Max.
Unit
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