i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
56
Freescale Semiconductor
3.7.6.1
ESDCTL Electrical Specifications
3.7.6.1.1
SDRAM Memory Controller
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
SDRAM.
Figure 25. SDRAM Read Cycle Timing Diagram
Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Unit
SD1
SDRAM clock high-level width1
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level widt
h1tCL
3.4
4.1
ns
SD3
SDRAM clock cycle time
tCK
7.5
—
ns
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.0
—
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.8
—
ns
SDCLK
WE
ADDR
DQ
DQM
COL/BA
Data
CS
CAS
RAS
Note: CKE is high during the read/write cycle.
SD4
SD1
SD3
SD2
SD4
SD5
SD6
SD7
SD10
SD8
SD9
SDCLK
ROW/BA