
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
73
Figure 42. Synchronous Memory TIming Diagram for Burst Write Access—
BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
Figure 43. Muxed A/D Mode Timing Diagram for Synchronous Write Access—
WSC=7, LBA=1, LBN=1, LAH=1
Last Valid Addr
BCLK
ADDR
DATA
CS[x]
RW
LBA
OE
EB[y]
ECB
Address V1
V1
V1+4
V1+12
V1+8
WE12
WE4
WE5
WE6
WE7
WE8
WE9
WE13
WE14
WE16
WE17
WE22
WE24
WE15
Write
BCLK
ADDR/
RW
LBA
OE
EB[y]
CS[x]
Address V1
Write Data
Last Valid Addr
M_DATA
WE4
WE5
WE6
WE7
WE9
WE8
WE12
WE13
WE14
WE15
WE16
WE17