參數(shù)資料
型號(hào)： MCHRC705KJ1CPE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 62/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU 1.2K 4MHZ OTP 16-DIP
標(biāo)準(zhǔn)包裝： 25
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 10
程序存儲(chǔ)器容量： 1.2KB（1.2K x 8）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-DIP（0.300"，7.62mm）
包裝： 管件
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
57
Chapter 6
Low-Power Modes
6.1 Introduction
The MCU can enter the following low-power standby modes:
Stop mode — The STOP instruction puts the MCU in its lowest power-consumption mode.
Wait mode — The WAIT instruction puts the MCU in an intermediate power-consumption mode.
Halt mode — Halt mode is identical to wait mode, except that an oscillator stabilization delay of 1
to 4064 internal clock cycles occurs when the MCU exits halt mode. The stop-to-wait conversion
bit, SWAIT, in the mask option register, enables halt mode.
Enabling halt mode prevents the computer operating properly (COP) watchdog from being
inadvertently turned off by a STOP instruction.
Data-retention mode — In data-retention mode, the MCU retains RAM contents and CPU register
contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but the CPU cannot execute
instructions.
6.2 Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the program counter with the reset vector
or with an interrupt vector:
Exiting Stop Mode
External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the
program counter with the contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an
enabled port A external interrupt pin starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Exiting Wait Mode
External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the
program counter with the contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an
enabled port A external interrupt pin starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
COP watchdog reset — A timeout of the COP watchdog resets the MCU, starts the CPU clock, and
loads the program counter with the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow interrupt requests start the MCU
clock and load the program counter with the contents of locations $07F8 and $07F9.
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