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| 型號(hào)： | MCHRC705KJ1CPE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 20/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 1.2K 4MHZ OTP 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 10 |
| 程序存儲(chǔ)器容量： | 1.2KB（1.2K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | OTP |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
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Pin Functions
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
19
1.4.2.4 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-8. This configuration is possible regardless of whether
the crystal/ceramic resonator or the RC oscillator is enabled.
Figure 1-8. External Clock Connections
1.4.3 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An internal reset also pulls
the RESET pin low. An internal resistor to VDD pulls the RESET pin high. A steering diode between the
RESET and VDD pins discharges any RESET pin voltage when power is removed from the MCU. The
RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to
Chapter 8 Resets and Interrupts for more information.
1.4.4 IRQ/VPP
The external interrupt/programming voltage pin (IRQ/VPP) drives the asynchronous IRQ interrupt function
of the CPU. Additionally, it is used to program the user EPROM and mask option register. (See
The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative
edge-sensitive and low level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/VPP input requires an external resistor to VDD for wired-OR
operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The
voltage on this pin should not exceed VDD except when the pin is being used for programming the
EPROM.
NOTE
The mask option register can enable the PA0–PA3 pins to function as
external interrupt pins.
1.4.5 PA0–PA7
These eight input/output (I/O) lines comprise port A, a general-purpose bidirectional I/O port. (See
Chapter 5 External Interrupt Module (IRQ) for information on PA0–PA3 external interrupts.)
1.4.6 PB2 and PB3
These two I/O lines comprise port B, a general-purpose bidirectional I/O port.
MCU
EXTERNAL
CMOS CLOCK
OSC1
OSC2
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