參數(shù)資料
型號: MCF5484CZP200
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388
文件頁數(shù): 69/96頁
文件大?。?/td> 2006K
代理商: MCF5484CZP200
MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
71
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
A.3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD
pins. The filter shown in Figure 22 should be connected between the board VDD and the PLL VDD
pins. The resistor and capacitors should be placed as close to the dedicated PLL VDD pin as
possible.
Figure 22. System PLL VDD Power Filter
A.3.2
USB Power Filtering
To minimize noise, a external filters are required for each of the USB power pins. The filter shown in
Figure 23 should be connected between the board EVDD or IVDDand each of the USB VDD pins. The
resistor and capacitors should be placed as close to the dedicated USB VDD pin as possible. A separate filter
circuit should be included for each USB VDD pin, a total of five circuits.
Figure 23. USB VDD Power Filter
Lists the resistor values and supply voltages to be used in the circuit for each of the USB VDD pins.
Output low voltage IOL =8 mA , 16 mA ,24 mA
5
VOL
—0.5
V
Capacitance 2, Vin =0 V, f = 1 MHz
CIN
—TBD
pF
1
IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure 22 for an
example circuit. Note: There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input.
2
Capacitance CIN is periodically sampled rather than 100% tested.
Table 22. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Units
Board VDD
10
0.1 F
PLL VDD Pin
10 F
GND
Board EVDD/IVDD
R
0.1 F
USB VDD Pin
10 F
GND
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