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| 型號： | MCF5484CZP200 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, BGA-388 |
| 文件頁數(shù)： | 67/96頁 |
| 文件大?。?/td> | 2006K |
| 代理商： | MCF5484CZP200 |
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MOTOROLA
MCF548x Integrated Microprocessor Hardware Specifications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MCF548x Family Features
1.4.1
ColdFire V4e Core Overview
The ColdFire V4e core is a variable-length RISC, clock-multiplied core that includes a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities. The
limited superscalar design approaches dual-issue performance with the cost of a scalar execution pipeline.
The ColdFire V4e processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer. The four-stage instruction fetch pipeline (IFP) prefetches the instruction stream, examines it to
predict changes of flow, partially decodes instructions, and packages fetched data into instructions for the
operand execution pipeline (OEP). The IFP can prefetch instructions before the OEP needs them,
minimizing the wait for instructions. The instruction buffer is a 10 instruction, first-in-first-out (FIFO)
buffer that decouples the IFP and OEP by holding prefetched instructions awaiting execution in the OEP.
The OEP includes five pipeline stages: the first stage decodes instructions and selects operands (DS), and
the second stage generates operand addresses (OAG). The third and fourth stages fetch operands (OC1 and
OC2), and the fifth stage executes instructions (EX).
The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to
the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE)
Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit,
double-precision floating point data and supports single-precision and signed integer input operands. The
FPU programming model is like that in the MC68060 microprocessor. The FPU is intended to accelerate
the performance of certain classes of embedded applications, especially those requiring high-speed floating
point arithmetic computations.
The ColdFire V4e processor also incorporates the ColdFire memory management unit (MMU), which
provides virtual-to-physical address translation and memory access control. The MMU consists of
memory-mapped control, status, and fault registers that provide access to translation lookaside buffers
(TLBs). Software can control address translation and access attributes of a virtual address by configuring
MMU control registers and loading TLBs. With software support, the MMU provides demand-paged,
virtual addressing.
The ColdFire V4e core implements the ColdFire instruction set architecture revision B with support for
floating Point instructions. Additionally, the ColdFire V4e core includes the enhanced multiply-accumulate
unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution
pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported
operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands and a
complete set of instructions to process these data types. The EMAC provides superb support for execution
of DSP operations within the context of a single processor at a minimal hardware cost.
1.4.2
Debug Module (BDM)
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators.
The MCF548x debug module provides support in three different areas:
Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.
相關(guān)PDF資料 |
PDF描述 |
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| MCF5485CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5483CVR166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5481CZP166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
| MCF5484CVR200 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388 |
| MCF5481CVR166 | 32-BIT, 166.66 MHz, RISC PROCESSOR, PBGA388 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5485 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF5485CVR200 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5485CZP200 | 功能描述:微處理器 - MPU MCF548X V4ECORE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF548X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
| MCF548X_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor |
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