參數(shù)資料
型號(hào)： MCF547X
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： MCF547x Integrated Microprocessor Electrical Characteristics
中文描述： MCF547x集成的微處理器，電氣特性
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 706K
代理商： MCF547X
FlexBus
MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2
Freescale Semiconductor
9
8.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
Table 10. FlexBus AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
30
66
Mhz
1
NOTES:
1
The frequency of operation is the same as the PCI frequency of operation. The MCF547X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.
2
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3
Timing for chip selects only applies to the FBCS[5:0] signals. Please see
Section 9.2, “DDR SDRAM AC
Timing Characteristics
” for SDCS[3:0] timing.
4
The FlexBus supports programming an extension of the address hold. Please consult the MCF547X
specification manual for more information.
5
These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.
FB1
Clock Period (CLKIN)
15.15
33.33
ns
2
FB2
Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
—
7.0
ns
3
FB3
Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
1
—
ns
3
, 4
FB4
Data Input Setup
3.5
—
ns
FB5
Data Input Hold
0
—
ns
FB6
Transfer Acknowledge (TA) Input Setup
4
—
ns
FB7
Transfer Acknowledge (TA) Input Hold
0
—
ns
FB8
Address Output Valid (PCIAD[31:0])
—
7.0
ns
5
FB9
Address Output Hold (PCIAD[31:0])
0
—
ns
5
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